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ISSCC 2013Session 15 · DATA CONVERTER TECHNIQUESData Converters

A 20b Clockless DAC with Sub-ppm-Linearity 7.5nV/√Hz-Noise and 0.05ppm/°C-Stability

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📋 论文概要

该论文提出了一种20位无时钟DAC,采用分段电压模式R-2R架构,实现了亚ppm线性度、7.5nV/√Hz低噪声和0.05ppm/°C低温漂,适用于医疗成像和科学仪器等对噪声和稳定性要求极高的应用。

💡 主要创新点

核心指标
20位分辨率,亚ppm线性度,7.5nV/√Hz噪声,0.05ppm/°C温度稳定性
重要性
发表年份
ISSCC 2013

🏷 关键词

无时钟DAC高精度低噪声低温漂R-2R

📄 原文摘要

Douglas Chisholm1, Denise T. Lee1 Analog Devices, Edinburgh, United Kingdom, Analog Devices, Wilmington, MA 1 2 DACs without continuous clocking are often favored in applications such as medical imaging and scientific instrumentation. The DACs in these high-precision systems are commonly endpoint-calibrated. After this calibration, a non-ideal DAC contributes three main sources of error: noise, temperature drift, and INL. The segmented voltage-mode R-2R DAC is an attractive architecture for reducing the first two of these error sources. Resistor Johnson noise is fixed by the DAC’s code-independent output resistance, which is readily lowered by the combination of several parallel segments. The complete signal path can be built using opamps that have a minimal noise gain of unity. This architecture also benefits from inherently zero endpoint error, avoiding any gain or offset drift over temperature.

👥 作者与机构

Roddy C. McLachlan1, Alan Gillespie1, Michael C. W. Coln2,

分类:Data Converters · 年份:ISSCC 2013