A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N Phase Locked-Loop Using a Phase-Interpolating Phase-to-Digital Converter

📋 论文概要

该论文提出了一种面积为0.026mm²、功耗5.3mW的32-2000MHz数字小数-N锁相环，采用相位插值相位-数字转换器，解决了全数字PLL噪声大、功耗高以及混合方法中模拟电路设计困难的问题。

💡 主要创新点

• 提出一种基于相位插值的相位-数字转换器，实现了宽频率范围的高分辨率相位检测。
• 采用全数字架构结合相位插值技术，在极低面积和功耗下实现了小数分频功能。

🏷 关键词

📄 原文摘要

from analog circuits to their digital counterparts, with digital PLLs (DPLLs) being an example of this trend [1]. All-digital or fully synthesizable approaches, which exploit the merits of advanced processes, suffer from poor noise performance and high power consumption [2]. On the other hand, hybrid approaches, which employ analog components such as digital-to-analog converters (DACs), digitalto-time converters, phase interpolators (PIs) and regulators, have the typical difficulties associated with analog circuits, such as low output resistance, small voltage headroom and large variation. In this paper, we propose a highly digital architecture for a DPLL – one which minimizes the design effort typically required for analog circuits. The power and area-consuming circuits in prior

👥 作者与机构

Tae-Kwang Jang, Xing Nan, Frank Liu, Jungeun Shin, Hyungreal Ryu,

Jihyun Kim, Taeik Kim, Jaejin Park, Hojin Park Samsung Electronics, Yongin, Korea Recent innovations in semiconductor processes have accelerated the transition