A 0.45V 100-Channel Neural-Recording IC with Sub-μW/Channel Consumption in 0.18μm CMOS

📋 论文概要

本文提出了一种采用DR折叠技术的功率高效神经记录架构，实现了0.45V超低电压操作和每通道亚微瓦级功耗，解决了传统神经记录系统中噪声效率与功耗之间的权衡问题。该芯片集成了100个记录通道，在0.18μm CMOS工艺中制造。

💡 主要创新点

• 提出了DR折叠技术，允许在低电压下保持足够的动态范围，从而降低功耗。
• 实现了0.45V的极低电源电压和每通道亚微瓦级功耗，同时支持100通道并行记录。
• 通过创新的电路设计，在0.18μm CMOS工艺中实现了高性能神经记录，无需先进工艺节点。

🏷 关键词

📄 原文摘要

Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage is determined by a DR requirement at the analog recording chain output that limits the maximum achievable resolution of the A-to-D conversion. In this paper, a power-efficient neural-recording architecture using a DR-folding technique is presented to enable low-voltage operation without compromising the DR performance. The proposed architecture can operate with only half of the typically required supply voltage, which results in about 50% power reduction.

👥 作者与机构

Dong Han1,2, Yuanjin Zheng1, Ramamoorthy Rajkumar3, Gavin Dawe3,

Minkyu Je2,3 Nanyang Technological University, Singapore, Singapore Institute of Microelectronics, Singapore, Singapore 3 National University of Singapore, Singapore, Singapore 1 2