A 0.1pJ/b 5-to-10Gb/s Charge-Recycling Stacked Low-Power I/O for On-Chip Signaling in 45nm CMOS SOI

📋 论文概要

该论文提出了一种用于片内信号传输的电荷回收堆叠低功耗I/O接口，工作在5至10Gb/s速率下，能效达到0.1pJ/b。通过电荷回收技术和堆叠结构显著降低了功耗，解决了高速片内互连的能耗问题。

💡 主要创新点

• 采用电荷回收堆叠技术，通过复用电源电压降低动态功耗。
• 引入弱上拉晶体管和尾晶体管等电路改进，提升接收器稳定性和减少短路电流。

🏷 关键词

📄 原文摘要

J. Watson, Yorktown Heights, NY, in transparent mode and the other is in data latching mode. The output stability is improved by newly-introduced weak pull-up transistor M7 that helps maintain the voltage level of node GDB when GD=0 (GDB=VDD) in evaluation mode (CLK=0, CLK1=CLK2=VDD). Finally, by adding tail transistor M6, short-circuit current is reduced when GD is high in precharge mode (CLK=VDD, CLK1=CLK2=0). These design enhancements result in a significant improvement in RX performance over that of the previous design in [6]. 1 *now at National Tsing Hua University, Hsinchu, Taiwan, **now at Apple, Cupertino, CA Compact low-power signaling schemes to drive on-chip interconnects are needed for processor chips where high-bandwidth data buses connect processor cores and on-chip cache. Since a significant portion of the signaling power is

👥 作者与机构

Yong Liu1, Ping-Hsuan Hsieh*, Seongwon Kim1, Jae-sun Seo1,

Robert Montoye1, Leland Chang1, Jose Tierno**, Daniel Friedman1 IBM T