A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS

📋 论文概要

本文提出了一种14位80MS/s的逐次逼近寄存器（SAR）模数转换器（ADC），采用65nm CMOS工艺实现了73.6dB的SNDR。该设计解决了SAR架构在高速高精度应用中难以同时兼顾速度和精度的难题。

💡 主要创新点

• 采用异步时序和冗余决策技术，在不牺牲速度的情况下提高精度
• 通过优化比较器噪声和电容匹配，实现了高线性度和低噪声性能

🏷 关键词

📄 原文摘要

veryhigh-SNR applications where the precision and stability of capacitors are leveraged along with the use of large signal swings [1], and (b) in high-speed, lowresolution applications [2, 3] in which the SAR’s low power and simplicity has enabled high levels of time-interleaving. In between, ADCs with greater than 10 effective bits and sample rates above 20MS/s are typically not based on the SAR architecture. The sequential nature of the SAR algorithm makes it difficult to achieve both high speed and high accuracy, as increasing the resolution requires each bit decision to be both faster and lower noise. This paper presents a SAR that overcomes some of the conventional speed limitations; it uses a 1.2V-only supply and achieves >70dB SNDR at 80MS/s, which extends the state of the art

👥 作者与机构

Ron Kapusta1, Junhua Shen1, Steven Decker1, Hongxing Li2, Eitake Ibaragi2

Analog Devices, Wilmington, MA, 2Analog Devices, Tokyo, Japan 1 Successive-approximation ADCs (SARs) have excelled in two spaces: (a) in