An 8Gb/s 0.65mW/Gb/s Forwarded-Clock Receiver Using an ILO with Dual Feedback Loop and Quadrature Injection Scheme

📋 论文概要

提出一种采用双反馈环路和正交注入方案的注入锁定振荡器（ILO）的转发时钟接收机，实现了8Gb/s数据率和0.65mW/Gb/s的功耗效率，解决了低功耗和高带宽下时钟恢复的挑战。

💡 主要创新点

• 采用双反馈环路结构，结合频率锁定和相位锁定，提高了ILO的抖动跟踪带宽和稳定性
• 提出正交注入方案，利用正交相位注入增强注入锁定效率，降低功耗

🏷 关键词

📄 原文摘要

low power consumption while achieving high aggregate bandwidth is the key trend. Forwarded-clock (FC) architecture is well suited to this trend because of the simple structure and inherent correlation of clock and data jitter [1]. Clock-recovery circuits consume a large portion of the I/O power. PLL/DLLs with a phase interpolator are widely used for the clock recovery circuits. However, they dissipate high power and jitter-tracking bandwidth (JTB) is low (PLL) or high (DLL), degrading the jitter correlation between data and clock. Recently, injection-locked oscillators (ILOs) have drawn much attention for the clock-recovery circuit of the FC interfaces due to their low power consumption [3-6]. By de-tuning the free-running frequency

👥 作者与机构

Ji-Hwan Seol1, Young-Ju Kim1, Sang-Hye Chung1, Kyoung-Soo Ha2,

Seung-Jun Bae2, Jung-Bae Lee2, Joo Sun Choi2, Lee-Sup Kim1 KAIST, Daejeon, Korea, 2Samsung Electronics, Hwasung, Korea 1 For chip-to-chip parallel interfaces, maintaining