A 100GB/s Wide I/O with 4096b TSVs Through an Active Silicon Interposer with In-Place Waveform Capturing

📋 论文概要

该论文提出了一种通过有源硅中介层实现4096个TSV的宽I/O接口，达到100GB/s的数据带宽，并集成了原位波形捕获功能，用于解决3D堆叠内存系统中的高带宽、低功耗和可测试性问题。

💡 主要创新点

• 采用4096个TSV通过有源硅中介层实现宽I/O接口，显著提升数据带宽至100GB/s。
• 集成原位波形捕获功能，能够在芯片内部实时监测信号质量，增强可测试性和调试能力。
• 有源硅中介层不仅提供互连，还支持主动信号调理和测试功能，提升系统整体性能和可靠性。

🏷 关键词

📄 原文摘要

dimensional (3D) stacking of memory chips is a promising direction for implementing memory systems in mobile applications [1-2] and for low-cost high-performance computation [3]. The requirements are extremely low power consumption, high data bandwidth, stability and scalability of operation, as well as large storage capacity with a small footprint. A digital control chip at the base of the stack is needed to efficiently access the 3D memory hierarchy, as well as to emulate a standard memory interface for compatibility. The overall performance and yields of a 3D system are constrained by vertical communication channels among the stacked chips, as well as the connections to the PCB. However, the empirical models presently used in the design stage do not properly represent the electrical and mechanical properties and performance

👥 作者与机构

Satoshi Takaya1, Makoto Nagata1, Atsushi Sakai2, Takashi Kariya2,

Shiro Uchiyama2, Harufumi Kobayashi2, Hiroaki Ikeda2 Kobe University, Kobe, Japan, Association of Super-Advanced Electronics Technologies, Tokyo, Japan 1 2 Three