⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种可扩展的64通道并行I/O系统，在32nm CMOS工艺下实现了0.128至1Tb/s的聚合带宽和0.8至2.6pJ/b的能效，解决了高性能计算系统中对高带宽、低功耗和低成本I/O的需求。
Tzu-Chien Hsueh1, Sudip Shekhar1, Ganesh Balamurugan1, Frank O’Mahony1, Clark Roberts1, Randy Mooney2, Bryan Casper1 Intel, Hillsboro, OR, 2Intel, Mapleton, UT 1 High-performance computing (HPC) systems demand aggressive scaling of memory and I/O to achieve multiple terabits/sec of bandwidth. Minimizing I/O cost, area and power are crucial to achieving a practically realizable system with such large bandwidth. To meet these needs, we developed a low-power dense 64-lane I/O system with per-port aggregate bandwidth up to 1Tb/s and 2.6pJ/bit power efficiency. We developed a high-density connector and cable, attached to the top side of the package that enables this high interconnect density. A lanefailover mechanism provides design robustness for fault-tolerance. To further optimize power efficiency, the lane data rate scales from 2 to 16Gb/s with nonlinear power efficiency of 0.8 to 2.6pJ/bit, providing scalable aggregate bandwidth of 0.128 to 1Tb/s. Highly power scalable circuits such as
Mozhgan Mansuri1, James E. Jaussi1, Joseph T. Kennedy1,