A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR Enhancement Techniques Utilizing Noise

📋 论文概要

该论文提出了一种利用噪声的SAR ADC，通过噪声整形和动态比较器技术，在50MS/s采样率下实现了71dB SNDR，功耗仅4.2mW，解决了中速高精度SAR ADC功耗过高的问题。

💡 主要创新点

• 提出了一种噪声整形技术，利用比较器噪声和电容失配噪声来提升信噪比，无需额外功耗。
• 采用动态比较器与噪声耦合电路，在低功耗下实现高精度量化。

🏷 关键词

📄 原文摘要

utilizes the high switching speed of nanometer CMOS processes. In recent reports, time-interleaving techniques and multi-bit-per-cycle conversion have boosted speed to the GHz sampling range at low power consumption. However, to achieve SNR of >70dB at moderate sampling speed, SARs still need a lot of power, namely tens of mW [1-2]. In [1], a very high SNR of 90dB is achieved by a stage to amplify residue charge, which is one of the reasons for the 105mW power consumption at 12.5MS/s. In [2], 8× oversampling and a static current pre-amplifier for the comparator improve SNR to 88dB, but the ADC still consumes 66mW. In [3], digital calibration achieves an SNDR of 71dB at 3mW, but double conversion limits the sampling speed to 22.5MS/s.

👥 作者与机构

Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando,

Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho Panasonic, Moriguchi, Japan SAR-ADC power efficiency has improved due to its digitally oriented nature that