Intermittent Resonant Clocking Enabling Power Reduction at any Clock Frequency for 0.37V 980kHz Near-Threshold Logic Circuits

📋 论文概要

本文提出间歇谐振时钟（IRC）技术，通过在近阈值电压（0.37V）下使用脉冲式时钟信号替代传统50%占空比时钟，实现了任意时钟频率下的功耗降低。该技术在980kHz时钟频率的32x32位加法器阵列中得到验证，展现了低电压下的能效优势。

💡 主要创新点

• 首次提出间歇谐振时钟（IRC）技术，利用脉冲式时钟信号（非50%占空比）实现时钟频率无关的功耗降低，解决了传统谐振时钟在宽频率范围下能效受限的问题。
• 在0.37V近阈值电压下，采用静态CMOS锁存器代替触发器，适应IRC的脉冲时钟特性，并实现了最低能量工作点。

🏷 关键词

📄 原文摘要

37V near-Vt adder array. Fig. 24.9.3(b) shows a block diagram of a test chip. 32 arrays of 32b adders are implemented with input/output latches. The critical path of each adder is 110 FO4 inverter delays. In IRC, static CMOS latches, instead of flip-flops, are used, since CKB is not a signal with a 50% duty cycle but a pulse signal, as shown in Fig. 24.9.2(c). In this paper, VDD = 0.37V is used, because the measured minimum energy of the adder array is achieved at VDD = 0.37V. 1 2 In order to improve the energy efficiency of logic circuits, reductions in capacitance (C) and power supply voltage (VDD) are required, as energy consumption is proportional to CVDD2. Near-threshold (Vt) operation achieves an energy minimum [1]. Resonant clocking [2-5] can reduce the effective capacitance of the

👥 作者与机构

Hiroshi Fuketa1, Masahiro Nomura2, Makoto Takamiya1, Takayasu Sakurai1

University of Tokyo, Tokyo, Japan, Semiconductor Technology Academic Research Center, Yokohama, Japan The proposed IRC is applied to a 0