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ISSCC 2013Session 20 · FREQUENCY GENERATIONClocking & PLLs65nm CMOS

A 57.9-to-68.3GHz 24.6mW Frequency Synthesizer with In-Phase Injection-Coupled QVCO in 65nm CMOS

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📋 论文概要

该论文提出了一种基于同相注入耦合正交VCO(QVCO)的57.9-68.3GHz频率合成器,采用65nm CMOS工艺,功耗仅24.6mW。解决了毫米波频段正交LO信号生成困难、传统方法功耗高或难以实现的问题。

💡 主要创新点

工艺节点
65nm CMOS
重要性
发表年份
ISSCC 2013

🏷 关键词

频率合成器注入锁定正交VCO毫米波低功耗

📄 原文摘要

systems such as 60GHz band applications, the requirements of PLLs keep getting higher. In a mm-Wave direct-conversion transceiver, the quadrature LO signal generation is challenging. The conventional techniques to generate quadrature LO signals suffer from many problems. The method of using a divide-by-2 divider after a VCO with double LO frequency is popular in multi-GHz designs, but it is difficult to be realized at mm-Wave frequencies. Employing passive RC complex filters is another way to generate quadrature signals, but high power is required to compensate its loss. The conventional parallel-coupled QVCO seems to be a good choice for mm-Wave application. However, the approach suffers from poor phase noise. This work presents a fully integrated 57.9-to-68.3GHz

👥 作者与机构

Xiang Yi, Chirn Chye Boon, Hang Liu, Jia Fu Lin, Jian Cheng Ong, Wei Meng Lim

Nanyang Technological University, Singapore, Singapore Under the influence of increasing demand for high-data-rate communication

分类:Clocking & PLLs · 年份:ISSCC 2013