An Adaptive-Bandwidth PLL for Avoiding Noise Interference and DFE-Less Fast Precharge Sampling for over 10Gb/s/pin Graphics DRAM Interface

📋 论文概要

本文提出了一种自适应带宽PLL，通过动态调整带宽避免电源噪声干扰，以及一种无DFE的快速预充电采样技术，用于超过10Gb/s/pin的图形DRAM接口，有效降低抖动并提高数据采样余量。

💡 主要创新点

• 提出自适应带宽PLL，根据电源噪声频率自动调整带宽，避免噪声引起抖动峰值。
• 采用无DFE的快速预充电采样技术，减少电路复杂度并实现高速数据接收。

🏷 关键词

📄 原文摘要

GDDR interface [1,4]. As the bit rate increases, jitter of PLL, data-sampling margin, crosstalk and intersymbol interference (ISI) needs considerable management [1,3,5]. Moreover, as the supply voltage decreases, the self-generated internal noise of DRAM increases due to low efficiency of the internal voltage generator, especially the VPP voltage generator [2]. In general, the sensitivity of PLL to supply noise gives rise to large jitter accumulation. If the supply noise frequency is close to the PLL bandwidth, more jitter peaking occurs. Therefore, the PLL bandwidth is an important parameter to achieve low jitter performance [3]. Crosstalk becomes a crucial issue for over 7Gb/s GDDR interface [1]. However, the complexity of the transmitter and

👥 作者与机构

Junyoung Song1, Hyun-Woo Lee2, Soo-Bin Lim1, Sewook Hwang1,

Yunsaing Kim2, Young-Jung Choi2, Byong-Tae Chung2, Chulwoo Kim1 Korea University, Seoul, Korea, 2Hynix Semiconductor, Icheon, Korea 1 DRAM speed already reaches 7Gb/s/pin for