Self-Super-Cutoff Power Gating with State Retention on a 0.3V 0.29fJ/Cycle/Gate 32b RISC Core in 0.13μm CMOS

📋 论文概要

本文提出一种自超截止电源门控技术，结合状态保持，在0.3V超低电压下实现32位RISC核心，解决了超低电压设计中泄漏功耗与性能的矛盾，达到0.29fJ/cycle/gate的能效。

💡 主要创新点

• 提出自超截止电源门控（Self-Super-Cutoff Power Gating），利用自身信号增强截止效果，有效降低泄漏电流。
• 集成状态保持功能，在电源门控模式下保留寄存器状态，实现快速唤醒，适用于间歇工作场景。

🏷 关键词

📄 原文摘要

Using ultra low-voltage (ULV) is a viable approach towards lowering power consumption. However, due to the narrowing gap between the supply voltage and the threshold voltage, ULV designs inevitably suffer from either low performance or high leakage [1, 2]. Specifically, for applications that demand performance, low-threshold devices must be used and so leakage remains a significant problem. The most effective approach to cutting down leakage is power gating. In this regard, the SCCMOS [3] (Fig. 24.4.1, left) uses additional boost signals to “super cutoff” the leakage current. In SCCMOS, a charge pump is used to generate the boost signal, and the pump has to be on during the standby period to maintain the boost signal. As such, the leakage saved by the super cutoff may be far less than that consumed by the charge pump, negating the power advantages of ULV SCCMOS. This paper presents a self-super-cutoff (SSC) power gating technique that completely eliminates the problem of the charge pum

👥 作者与机构

Jian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang

National Chung Cheng University, Chaiyi, Taiwan