⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文针对先进CMOS工艺中PVT变化导致的时序裕度问题，提出了一种名为Razor-Lite的侧信道错误检测寄存器。通过该寄存器实时检测时序错误，实现动态时序裕度恢复，从而提升性能或降低能耗。
University of Michigan, Ann Arbor, MI Advanced CMOS technologies are highly susceptible to process, voltage, and temperature (PVT) variations due to sub-wavelength lithography and other manufacturing challenges. These variations cause performance uncertainty for which timing margins must be added to guarantee correct operation. Ultimately, this results in lost performance or energy: performance is lost directly through reduced clock frequency, while energy is sacrificed by operating at a higher voltage than necessary to meet non-margined timing requirements. Error detection and correction (EDAC) systems monitor critical paths with specialized registers. These registers detect late-arriving input transitions and trigger a state rollback. Reliably accomplishing this while minimizing overhead is a key challenge: both state and timing are required, adding to datapath and clock loading. Prior work uses either double sampling or a transition detector to detect
Seongjong Kim, Inyong Kwon, David Fick, Myungbo Kim, Yen-Po Chen, Dennis Sylvester