A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over Entire Nyquist Bandwidth

📋 论文概要

该论文提出了一款12位1.6GS/s的电流舵DAC，采用40nm CMOS工艺，功耗仅40mW。通过优化电流源阵列和开关瞬态，实现了在整个奈奎斯特带宽内SFDR超过70dB，解决了高速DAC中寄生电容和失配导致的线性度下降问题。

💡 主要创新点

• 采用新型电流源阵列设计，有效降低寄生电容对输出阻抗的影响，提升高频线性度。
• 优化开关时序和瞬态控制，减少输入码相关切换失真，改善SFDR性能。
• 在40nm CMOS工艺下实现低功耗与高速的平衡，达到1.6GS/s采样率仅40mW功耗。

📄 原文摘要

Current-steering DACs are generally used in high-speed signal generation. The critical challenges for DACs are to realize the highest-possible spurious-free dynamic range (SFDR) and inter-modulation distortion (IMD) at the widest possible signal bandwidth. However, the above performances are degraded by many nonlinear causes, e.g., parasitic capacitor-induced finite output impedance [1], current-source (CS) mismatch, and input-code dependent switching transients

👥 作者与机构

Wei-Te Lin, Tai-Haur Kuo

National Cheng Kung University, Tainan, Taiwan