A 45nm 6b/cell Charge-Trapping Flash Memory Using LDPC-Based ECC and Drift-Immune Soft-Sensing Engine

📋 论文概要

本文提出了一种采用45nm工艺的6b/cell电荷陷阱闪存，通过基于LDPC的纠错码和抗漂移软感测引擎，解决了多比特存储中阈值电压漂移导致的高原始误码率问题。

💡 主要创新点

• 实现了6b/cell的高密度电荷陷阱闪存技术，显著提升存储密度。
• 采用LDPC纠错码，有效纠正因分布漂移引起的高误码率。
• 提出抗漂移软感测引擎，动态调整感测电平以应对程序干扰、数据保持和温度变化。

🏷 关键词

📄 原文摘要

multiple-bits-per-cell technique is widely adopted. As presented in [1], a 4b/cell Flash memory by using error-detection (ED) scheme stores 2b data on two sides of a memory cell individually. Since the noise margin becomes smaller, the distribution drifts due to program disturb, data retention and temperature variation will cause higher raw bit-error-rate (RBER) if the sensing level (voltage) are not adjusted accordingly. The ED scheme can detect the drift direction by counting and storing the number of cells (Ni) with threshold voltage (VTH) below the ith sensing level (VREF i). A simple example with page size 1KB is demonstrated in Fig. 12.7.1. During a read operation, the number of cells (Ni, measured) whose VTH below VREF i is counted and compared to Ni. The ED scheme can find out a sub-optimal sensing lev

👥 作者与机构

Kin-Chu Ho1,2, Po-Chao Fang1, Hsiang-Pang Li1,

Cheng-Yuan Michael Wang1, Hsie-Chia Chang2 Macronix, Hsinchu, Taiwan, National Chiao Tung University, Hsinchu, Taiwan 1 2 To satisfy the demand of higher storage density, storing