32Gb/s 28nm CMOS Time-Interleaved Transmitter Compatible with NRZ Receiver with DFE

📋 论文概要

该论文提出了一种28nm CMOS工艺下的32Gb/s时间交织发射机，兼容带DFE的NRZ接收机。针对四分之一速率时钟占空比误差导致信号完整性下降的问题，在PLL和时钟分频器之间集成了占空比校正器（DCC），将半周期变化从±4.5ps抑制到±1.25ps。

💡 主要创新点

• 采用4路时间交织的四分之一速率时钟架构，实现32Gb/s高速数据传输。
• 在PLL与时钟分频器之间嵌入占空比校正器，有效抑制16GHz时钟的占空比误差，提升输出信号完整性。

🏷 关键词

📄 原文摘要

Fujitsu, Kawasaki, Japan, 4 Fujitsu Microelectronics Solutions, Akiruno, Japan Since the transmitter uses 4-way interleaved quarter-rate clocking to generate the output signal, the output signal integrity is prone to duty-cycle error in the 16GHz clock signal. To keep the duty ratio of the 16GHz clock from a phase locked loop (PLL), a duty-cycle corrector (DCC) [3] is implemented between a PLL and the clock divider. When the variation of the clock signal’s half-cycle length is ±4.5ps at the DCC input, the half-cycle variation at the DCC output is less than ±1.25ps at worst-case PVT condition. 1 2 Next-generation communication standards, such as OIF-CEI-25G-LR and IEEE P802.3bj, demand high-speed electrical backplane transceivers that support data

👥 作者与机构

Yuuki Ogata1, Yasuo Hidaka2, Yoichi Koyanagi1, Sadanori Akiya3,

Yuji Terao3, Kosuke Suzuki1, Keisuke Kashiwa4, Masanobu Suzuki4, Hirotaka Tamura1 Fujitsu Laboratories, Kawasaki, Japan, Fujitsu Laboratories of America, Sunnyvale, CA, 3