A 66Gb/s 46mW 3-Tap Decision-Feedback Equalizer in 65nm CMOS

📋 论文概要

本文提出了一种采用65nm CMOS工艺的3抽头判决反馈均衡器（DFE），实现了66Gb/s的数据率与仅46mW的低功耗。通过解决传统环路展开（loop-unrolling）DFE中因选择器MUX引入的额外延迟及复杂度指数增长问题，满足了高速I/O对均衡器性能的严苛需求。

💡 主要创新点

• 提出了适用于66Gb/s高速率的3抽头DFE架构，通过优化关键路径时序避免了传统环路展开带来的延迟和复杂度问题。
• 实现了在65nm CMOS工艺下46mW的超低功耗，在同类高速均衡器中具有显著的能效优势。

🏷 关键词

📄 原文摘要

Given the continuously climbing data rates of high-speed I/O’s, equalizer circuits—and particularly decision-feedback equalizer (DFE) designs—are being pushed to operate at ever-higher speeds. At 20 to 40Gb/s data-rates, loopunrolled DFEs are widely adopted to relieve the feedback timing constraints of the initial tap(s) [1]. However, loop-unrolling introduces additional delay into the critical paths of later (non-unrolled) DFE taps due to the selection MUXes, and with its exponential growth in complexity, does not scale well as the number of unrolled taps increases. Perhaps due to this challenge, no multi-tap DFE solutions with single pJ/bit efficiencies have yet been demonstrated at data rates >40Gb/s. Realizing an efficient multi-tap DFE at these data-rates leads us to re-examine techniques to directly close the 1st tap. First, as shown in Fig. 2.2.1, the latency of the feedback loop can be reduced to a single latch delay (Td-q) by merging

👥 作者与机构

Yue Lu, Elad Alon

University of California, Berkeley, CA