A Divider-Less Sub-Harmonically Injection-Locked PLL with Self-Adjusted Injection Timing

📋 论文概要

本文提出了一种无分频器的次谐波注入锁定PLL，通过自调整注入时序克服了工艺、电压和温度变化对注入时序的敏感性，同时降低了功耗。

💡 主要创新点

• 采用无分频器结构，消除了分频器的功耗，提高了能效。
• 引入自调整注入时序机制，自动补偿PVT变化，保证注入锁定稳定性。

🏷 关键词

📄 原文摘要

frequency synthesis, and data conversion. In [1,2], a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power. In [3-5], a low-phase-noise sub-harmonically injection-locked PLL (SIPLL) is presented. The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations [1-3,5]. In addition, the divider of a SIPLL [35] cannot be powered down to save the power as in [1,2]. In this paper, a divider-less SIPLL with self-adjusted injection timing is presented. Figure 23.8.1 shows our SIPLL. It includes a pulse generator, a timing-adjusted phase detector (PD), a charge pump (CP), and a conventional phase-locked loop (PLL). This conventional PLL is composed of a LC voltage-controlled oscillator

👥 作者与机构

I-Ting Lee1, Yen-Jen Chen2, Shen-Iuan Liu1, Chewn-Pu Jou2,

Fu-Lung Hsueh2, Hsieh-Hung Hsieh2 National Taiwan University, Taipei, Taiwan, 2TSMC, Hsinchu, Taiwan 1 A low-phase-noise phase-locked loop (PLL) is widely used in clock generation,