A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge-Average Switching DAC in 90nm CMOS

📋 论文概要

本文提出了一种采用电荷平均开关DAC（Charge-Average Switching DAC）的10位SAR ADC，在90nm CMOS工艺下实现0.5至4MS/s的采样率，每转换步能耗仅为2.4至5.2fJ，适用于无线传感器网络和生物医学设备等低功耗应用。该设计通过改进DAC开关策略显著降低了开关能量和SAR控制逻辑功耗，解决了传统SAR ADC中功耗瓶颈问题。

💡 主要创新点

• 提出电荷平均开关DAC技术，通过重新分配电容充电能量来减少开关切换功耗
• 实现极低能耗（2.4-5.2fJ/conversion-step），在中等分辨率SAR ADC中达到领先能效

🏷 关键词

📄 原文摘要

Applications of wireless sensor networks and biomedical devices frequently require an ADC with medium resolution (8 to 12b) running at hundreds of kS/s to a few MS/s. Successive-approximation register (SAR) ADCs show convincing performance with inherent low-power operation and high efficiency. DAC switching energy and SAR control logic are the main power-hungry blocks in ADC designs, and this attracts much research interest [1-6]. Set-and-down [1-3], step-wise [4], merged capacitor [5], and input-range-prediction [6] show improved switching-energy efficiency with design penalties such as commonmode shift, extra auxiliary capacitors, extra voltage reference (Vcm), and an extra conversion step, respectively. Reducing power with a smaller unit capacitance requires extra calibration to meet accuracy requirements [2-3]. Without the aforementioned drawbacks, this work presents a SAR ADC with FoM performance as low as 2.4fJ/conv-step, and a variable sampling rate optimized by adequately scali

👥 作者与机构

Chang-Yuan Liou, Chih-Cheng Hsieh

National Tsing Hua University, Hsinchu, Taiwan