An SRAM Using Output Prediction to Reduce BL-Switching Activity and Statistically-Gated SA for up to 1.9× Reduction in Energy/Access

📋 论文概要

本文提出一种利用输出预测减少位线开关活动的SRAM设计，并采用统计门控读出放大器(SA)技术，实现了高达1.9倍的能耗降低，主要针对移动应用中SRAM功耗瓶颈问题。

💡 主要创新点

• 提出输出预测机制，通过预测存储数据来减少位线不必要的翻转，降低动态功耗。
• 引入统计门控读出放大器，根据数据分布动态关断部分SA，进一步节省静态功耗。

🏷 关键词

📄 原文摘要

Mobile applications such as tablets pack increasingly more processing capability comparable to workstations or laptops but can do little for cooling or extending the battery life in their form factors. SRAMs account for a large fraction of chip area and are critical in this context. Recent work has focused on voltage scaling in SRAMs, which is an effective way of achieving energy efficiency [1,2]. These conventional SRAMs are mostly general-purpose in the sense that they are designed without considering the specific features of the data they will store. However, application-specific features such as statistics of storage data can be exploited and incorporated into the transistor-level design to provide a new dimension towards achieving the next level of energy savings in addition to the savings provided through voltage scaling. The work in [3] is an example where an inversion bit is added for each word to reduce read-bitline (RBL) transitions

👥 作者与机构

Mahmut E. Sinangil1, Anantha P. Chandrakasan2

Nvidia, Bedford, MA, 2Massachusetts Institute of Technology, Cambridge, MA