⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一种采用高度数字多比特量化器的连续时间ΔΣ调制器，在28nm CMOS工艺下实现了28fJ/conv-step的FoM、78dB动态范围和18MHz带宽，有效降低了量化器功耗。
compensation and high-order single-opamp integrators have achieved FoM values well below 100fJ/conv-step [1-3]. With loop-filter power greatly reduced, power dissipation in multibit quantizers becomes especially significant. For example, the quantizer in [2] accounts for 2.8mW of 8.5mW total power dissipation. Also, the input capacitance of multibit quantizers and the output parasitics of excess loop delay (ELD) compensation DACs result in increased power demand for summing circuits. To minimize power dissipation, two recent works use 1b quantizers with FIR DACs and replace ELD compensation DACs with a DAC followed by analog filter [3] or with feedback to the pre-amplifier [4]. ELD compensation may also be realized using digital logic following the quantizer [5]. This paper presents a low-power solution based on a highly digital multibit quantizer with embedded feedback to compensate for
Yun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu
MediaTek, Hsinchu, Taiwan Recently reported continuous-time (CT) ΔΣ modulators with opamp bandwidth