⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种用于先进封装的短距离串行链路，采用接地参考单端信号传输，在28nm CMOS工艺下实现了20Gb/s的数据率和0.54pJ/b的能效。接收器使用共栅放大器与CMOS反相器级联，实现低摆幅信号到全摆幅CMOS电平的转换和放大。
Thomas H. Greer III1, Stephen G. Tell1, C. Thomas Gray1 The receiver (right of Fig. 23.3.2) consists of a common-gate amplifier [3,4], biased so that its output swing is symmetric around the switching threshold of a CMOS inverter; it is followed by a CMOS inverter that acts as the second stage of amplification. The first stage has a gain of about 2 and also serves as the level converter from GRS to CMOS signal levels, and the second stage has a gain of about 5. The amplifier output can therefore directly drive conventional CMOS logic at full swing for a line amplitude of 100mV. Nvidia, Durham, NC, 2Nvidia, Santa Clara, CA 1 Laminated packages, silicon interposer substrates, and special-purpose package-to-package interconnect [1,5], together with 3D stacking of silicon components [2] enable systems with greatly improved computational power, memory capacity and bandwidth. These package options offer very high-bandwidth channels between chips on the same substrate. We employ ground-refere
John W. Poulton1, William J. Dally2, Xi Chen2, John G. Eyles1,