A 1.15Gb/s Fully Parallel Nonbinary LDPC Decoder with Fine-Grained Dynamic Clock Gating

📋 论文概要

该论文提出了一种全并行非二进制LDPC解码器，通过细粒度动态时钟门控技术实现了1.15Gb/s的吞吐量，解决了非二进制LDPC解码器高复杂度与低能效的问题。

💡 主要创新点

• 采用全并行架构实现非二进制LDPC解码，显著提升吞吐量。
• 引入细粒度动态时钟门控技术，降低动态功耗，提高能效。

🏷 关键词

📄 原文摘要

The primary design goal of a communication or storage system is to allow the most reliable transmission or storage of more information at the lowest signalto-noise ratio (SNR). State-of-the-art channel codes including turbo and binary LDPC have been extensively used in recent applications [1-2] to close the gap towards the lowest possible SNR, known as the Shannon limit. The recently developed nonbinary LDPC (NB-LDPC) code, defined over Galois field (GF), holds great promise for approaching the Shannon limit [3]. It offers better coding gain and a lower error floor than binary LDPC. However, the complex nonbinary decoding prevents any practical chip implementation to date. A handful of FPGA designs and chip synthesis results have demonstrated throughputs up to only 50Mb/s [4-6]. In this paper, we present a 1.15Gb/s fully parallel decoder of a (960, 480) regular-(2, 4) NB-LDPC code over GF(64) in 65nm CMOS. The natural bundling of global interconnects and an optimized placement permit 8

👥 作者与机构

Youn Sung Park, Yaoyu Tao, Zhengya Zhang

University of Michigan, Ann Arbor, MI