A 0.032mm2 3.1mW Synthesized Pixel Clock Generator with 30psrms Integrated Jitter and 10-to-630MHz DCO Tuning Range

📋 论文概要

该论文提出了一种用于数字电视和视频应用的合成像素时钟发生器，采用双环架构来降低环形振荡器DCO的相位噪声，实现了0.032mm2面积和3.1mW功耗，集成抖动为30psrms，DCO调谐范围为10-630MHz。

💡 主要创新点

• 采用双环架构（模拟环和数字主环）有效抑制环形振荡器DCO的相位噪声，解决了低输入频率下环路带宽受限导致的抖动问题。
• 实现了极小的芯片面积（0.032mm2）和低功耗（3.1mW），同时保持宽调谐范围和低抖动性能。

🏷 关键词

📄 原文摘要

digital TVs and also in other video applications. A low integrated jitter is required for good display quality. However, an extremely low input frequency coming from the horizontal synchronization signal (HSYNC) makes it difficult to achieve good jitter performance, because noise from the VCO cannot be sufficiently removed due to the limited loop bandwidth. In this work, a dual-loop architecture is adopted to reduce the phase noise from the VCO based on a ring oscillator. Prior work [1] proposed a dual-loop hybrid PLL composed of an analog loop for the DCO and the digital main loop. Unlike the hybrid architecture [1], our proposed PLL is composed of purely digital components and is synthesized in 28nm CMOS, including the TDC and the DCO, using a cell-based design methodology and

👥 作者与机构

Wooseok Kim1, Jaejin Park2, Jihyun Kim2, Taeik Kim2, HoJin Park2, DeogKyoon Jeong1

Seoul National University, Seoul, Korea, Samsung Electronics, Yongin, Korea 1 2 A pixel clock generator is widely utilized in the analog front-ends of