A 2.4psrms-jitter Digital PLL with Multi-Output BangBang Phase Detector and Phase-Interpolator-Based Fractional-N Divider

📋 论文概要

提出一种采用多输出Bang-Bang鉴相器和基于相位插值的分数分频器的数字锁相环，解决了传统Bang-Bang PLL仅能整数N操作的限制，实现了2.4psrms的低抖动性能。

💡 主要创新点

• 提出多输出Bang-Bang鉴相器架构，在不增加复杂度下提升相位检测精度。
• 利用相位插值器实现分数N分频，使Bang-Bang PLL具备分数N能力。
• 整体数字PLL架构低复杂度，避免了传统TDC的大功耗和面积开销。

🏷 关键词

📄 原文摘要

time-to-digital converter(TDC)-based architectures [1] to avoid significant complexity and power overhead due to such a critical building block [2-4]. Architectures based on bang-bang phase detectors are very attractive for their low-jitter, low-power capabilities, but are limited to integer-N operation by nature. Solutions that merge the key performance of the bang-bang architecture with fractional-N operation as in [3] are needed in order to turn the bang-bang digital PLLs into real alternatives to TDC-based PLLs. This paper presents a novel low-complexity bang-bang digital PLL architecture capable of fractional-N operation by means of a Phase-Interpolator(PI)-based fractional Feedback Divider, which allows accurate fractional division without background calibration (still needed in the approach shown in [3]). A 5b MultiOutput Bang-Bang Phase Detector (MOBBPD) is also introd

👥 作者与机构

Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt

Infineon Technologies, Villach, Austria In the field of digital PLLs, there is a trend to find alternatives to