⚡ 本页包含 AI 生成的分析内容，仅供参考
本文介绍了AMD的Jaguar低功耗x86-64核心，是Bobcat的后续产品，采用28nm工艺，面积3.08mm²，支持从平板电脑到客户端产品的宽功耗范围。通过集成电源门控和可调写入斩波技术，优化了SoC功耗并提高了RAM设计的灵活性和工艺可移植性。
in the standard place and route section. This allows for late changes to the RAMs without affecting the entire core and allows for easier process portability. AMD, Austin, TX “Jaguar” (JG) is the codename for AMD’s follow-on project to the low-power x86-64 core, codenamed “Bobcat” (BT). AMD’s first 28nm x86 processor, the 3.08mm² JG core is designed to support a wide range of applications from lowpower tablets requiring sub-5W SoCs to client products up to 25W. Similar to BT, the JG core uses integrated power gating to provide a low-power state for SOC power optimization. A JG compute unit (CU) is constructed using 4 JG cores, four 0.5MB L2 cache modules and an L2 interface (Fig. 3.4.1). An initial SOC has one 26.2mm² CU, but AMD’s modular design approach allows for different SOC configurations. JG has improvements over BT in IPC, frequency, and power. The load-store unit is redesigned for significant performance and power improvements over AMD’s
Teja Singh, Joshua Bell, Shane Southard, also includes an adjustable write-chop circuit which allows for silicon write-margin testing. The macros are built with strict flop edges to avoid feed-thru paths