An All-Digital PLL Using Random Modulation for SSC Generation in 65nm CMOS

📋 论文概要

该论文提出了一种采用高频随机调制（RM）而非低频周期调制的全数字锁相环（ADPLL），用于生成扩频时钟（SSC）。该方法显著降低了累积抖动（降低8倍），同时不影响EMI抑制或周期抖动，并允许减少或移除高速外设中的FIFO深度。

💡 主要创新点

• 首次在数字PLL中使用高频随机调制替代低频周期调制来生成扩频时钟，简化了实现并大幅降低累积抖动。
• 通过随机调制技术，在保持相同EMI抑制效果的同时，显著减少了FIFO深度需求，甚至可在低速接口中完全移除FIFO。

🏷 关键词

📄 原文摘要

This paper introduces a digital PLL which uses high-frequency random modulation (RM), as opposed to low-frequency periodic modulation, to generate a spread spectrum clock (SSC). The implementation is straightforward and reduces accumulated jitter substantially (by a factor of 8 in our implementation) with no penalty to EMI reduction or to period jitter. As a key advantage, the proposed design allows one to reduce the depth of FIFOs needed for high-data-rate peripherals or to remove it completely in case of low-data-rate interfaces. Reduction of EMI emissions is gaining importance in the automotive microcontroller area, due to increasing frequencies of operation and strict EMI limits. The state-of-the-art solution is to use PLLs which slowly modulate the clock frequency, reducing the peak spectral emission [1]. The modulation profile is mostly triangular and modulation frequencies are in the range of tens of kHz. In microcontrollers, a single source is typically used to produce the cloc

👥 作者与机构

Nicola Da Dalt, Peter Pridnig, Werner Grollitsch

Infineon Technologies, Villach, Austria