32Gb/s Data-Interpolator Receiver with 2-Tap DFE in 28nm CMOS

📋 论文概要

该论文提出了一种采用数据插值（Data-Interpolator）技术和2抽头判决反馈均衡器（DFE）的接收机，在28nm CMOS工艺下实现了32Gb/s的数据速率，解决了高速串行通信中的信号完整性问题和码间干扰。

💡 主要创新点

• 采用电荷共享方式实现数据插值，通过插值系数k调整采样间隔，在0.5UI的相邻切片间隔下完成1UI积分后产生内插电压。
• 集成2抽头DFE，有效消除信道的后标干扰，提升高速接收机的眼图张开度和误码率性能。

🏷 关键词

📄 原文摘要

Win Chaivipas1, Takushi Hashida1, Hiroki Miyaoka2, Masanori Hoshino3, Yoichi Koyanagi1, Takuji Yamamoto4, Sanroku Tsukamoto1, Hirotaka Tamura1 Fujitsu Laboratories, Kawasaki, Japan, Fujitsu Semiconductor, Yokohama, Japan, 3 Fujitsu Microelectronics Solutions, Yokohama, Japan, 4 Fujitsu Laboratories of America, Sunnyvale, CA is 1UI, whereas the sampling interval between adjacent DI slices is 0.5UI. After the 1UI integration is done, the even and odd samples are interpolated using charge sharing with the interpolation coefficient k. The interpolated voltages are given in Fig. 2.5.4, where Vin is the input voltage, gm is the value of transconductance, and tn is the nth sampling timing. The resolution of the data interpolation in terms of the timing is 6b/UI. Since the interpolation is performed on the static, analog samples stored on the capacitors, the DI achieves a wide operatingfrequency range of 12.5 to 32Gb/s.

👥 作者与机构

Yoshiyasu Doi1, Takayuki Shibasaki1, Takumi Danjo1,