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ISSCC 2011Session 8 · ARCHITECTURES & CIRCUITS FOR NEXT GENERATION WIRELINE TRANSCEIVERSWireline I/O

A Full-Duplex 10GBase-T Transmitter Hybrid with SFDR >65dBc Over 1 to 400MHz in 40nm CMOS

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📋 论文概要

该论文提出了一种用于10GBase-T以太网标准的全双工发射机与回声消除混合电路,通过DSP技术增强线性抵消和模拟非线性抵消,消除了对高线性度发射机的需求。采用40nm CMOS工艺实现,在1-400MHz带宽内实现残留失真<-65dBc和残留线性回声<-30dBc。

💡 主要创新点

发表年份
ISSCC 2011

📄 原文摘要

Teranetics, San Jose, CA A transmitter and echo cancellation hybrid for IEEE 802.3an 10GBase-T Ethernet standard is presented, that utilizes DSP techniques to enhance the linear cancellation, and analog non-linearity cancellation to eliminate the need of a high linearity transmitter. Implemented in 40nm CMOS, the transmitter has a residual distortion < –65dBc and residual linear echo < –30dBc over a bandwidth of 1 to 400MHz. The transmitter, including the echo-cancellation circuitry and on-chip DSP engine, consumes 250mW power and occupies 0.9mm2. The IEEE 802.3an 10GBase-T Ethernet standard requires full-duplex transmission and reception over each of the 4 twisted pairs in a 100m UTP cable. Both the transmitter and receiver operate in the same frequency band of 1 to 400MHz. This necessitates very good linear echo cancellation to ease the dynamic range requirements of receive circuitry, as well as very good transmitter distortion,

👥 作者与机构

Gaurav Chandra, Moshe Malkin

分类:Wireline I/O · 年份:ISSCC 2011