ISSCC 2011

2011

196 篇论文 · Wireline I/O (24) · Digital Processors (21) · Medical & Bio (18) · Data Converters (16)

ISSCC 2011 Session 1 Plenary
New Interfaces to the Body through ImplantableSystem Integration
Stephen Oesterle, Paul Gerrish, Peng Cong
Medtronic, Minneapolis, MN 1. Introduction The pace of technological change continues to enable new methods for interfacing with our world. An engine of that change has been the increasing capability in the electronics i
ISSCC 2011 Session 1 Plenary
Game-Changing Opportunities for Wireless Personal Healthcare and Lifestyle Jo De Boeck
imec, Leuven, Belgium & Holst Centre, Eindhoven, The Netherlands, 1.0 Introduction
In recent years, Personalized, Predictive, Preventive, and Participatory healthcare have become more than just buzzwords. Silicon is playing an important enabling role in this gradual, but certain revolution of our healt
ISSCC 2011 Session 1 Plenary
Eco-Friendly Semiconductor Technologies for Healthy Living Oh-Hyun Kwon
President, Samsung Electronics, Giheung, Korea, 2.1 Processors
Processors, often equated with human brains, are amongst the most sophisticated and complicated semiconductor logic devices available. Designing such processors is a very complicated task, which requires careful combinat
ISSCC 2011 Session 1 Plenary
February 21, 2011 / 10:50 AM Beyond the Horizon: The Next 10x Reduction in Power - Challenges and Solutions 10:50AM The energy efficiency of electronic circuits has dramatically improved over the past two decades. At the same time, computation, storage, and communication demands continue to grow with emerging wireless multimedia devices. In this inaugural Plenary Technology-Roundtable event, experts will discuss the opportunities to achieve the next order-of-magnitude reduction in energy consumption across various domains, including analog, digital, RF, and memory. The line between analog and digital continues to blur, as analog circuits are enhanced by applying digital corrections to compensate for increased analog component variability with process scaling. As well, digital will incorporate more analog to become more adaptive; for example, to optimize operating voltages at a fine-grain to match workloads and process variations. Memory circuits will need
to use a system-level approach which requires bit-cell optimization, low-voltage operation with integrated regulators, 3
materials for low-voltage digital circuits. TSVs will be important in reducing I/O power and the length of on-chip interconnects. For RF, integrated inductors and transformers with significantly lower resistance will be
ISSCC 2011 Session 10 Data Converters
A 480mW 2.6GS/s 10b 65nm CMOS Time-Interleaved ADC with 48.5dB SNDR up to Nyquist
Kostas Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard Van der Weide
many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die [1] could be simplified with a low-power 10b ADC that can digitize the e
NXP Semiconductors, Eindhoven, The Netherlands Trends in cable TV rece
ISSCC 2011 Session 10 Data Converters
A 12b 1GS/s SiGe BiCMOS Two-Way TimeInterleaved Pipeline ADC drives the top-plate sampling switch (M1) and achieves high SFDR. A 20Ω resistor between M1 and the 600fF sampling capacitor improves the linearity of M1.
Robert Payne1, Charles Sestok1, William Bright1, Manar El-Chammas1,
Marco Corsi1, David Smith1, Noam Tal2 Analog calibration techniques address the mismatches between branches. Timing skew is adjusted using a 10b DAC to supply the clock buffer power supply which changes its propagation d
ISSCC 2011 Session 10 Data Converters
An 800MS/s Dual-Residue Pipeline ADC in 40nm CMOS
Jan Mulder, Frank M.L. van der Goes, Davide Vecchi, Jan R. Westra,
Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult Broadcom, Bunnik, The Netherlands The 800MS/s 12b pipeline ADC presented here achieves a 59dB peak SNDR while consuming 105mW, resulting in an FOM of 0.18pJ/con
ISSCC 2011 Session 10 Data Converters
A 16b 80MS/s 100mW 77.6dB SNR CMOS Pipeline ADC
Janet Brunsilius1, Eric Siragusa1, Steve Kosic1, Frank Murden2,
increasingly requires high-performance ADCs that consume very little power. The 16b pipeline ADC described here achieves 77.6dBFS SNR, 77.6dBFS SNDR and 95dBc SFDR at 80MS/s with a 10MHz input. With a 200MHz input, the A
Ege Yetis1, Binh Luu1, Jeff Bray1, Phil Brown1, Allen Barlow1 1 Analog
ISSCC 2011 Session 10 Data Converters
A 0.024mm2 8b 400MS/s SAR ADC with 2b/Cycle and Resistive DAC in 65nm CMOS
Hegong Wei1, Chi-Hang Chan1, U-Fat Chio1, Sai-Weng Sin1,
Italy 2 The successive-approximation (SA) algorithm is traditionally used for lowbandwidth applications because it requires n clock cycles or more to obtain nbit resolution. However, the use of modern nanometer CMOS tech
Seng-Pan U1, Rui Martins1,2, Franco Maloberti3 1 University of Macau,
ISSCC 2011 Session 10 Data Converters
A Resolution-Reconfigurable 5-to-10b 0.4-to-1V Power Scalable SAR ADC
Marcus Yip, Anantha P. Chandrakasan
Applications such as sensor networks and medical monitoring often require ADCs that can digitize signals with varying bandwidth and dynamic range requirements. In energy-constrained systems, it is beneficial to adapt the
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2011 Session 10 Data Converters
A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz
Wei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu
The current-steering DACs are commonly used in generating high-frequency signals [1-4]. A current-steering DAC comprises current cells of various sizes. Each of them contains a current source and a current switch. The DA
National Chiao Tung University, Hsinchu, Taiwan
ISSCC 2011 Session 10 Data Converters
A 56GS/s 6b DAC in 65nm CMOS with 256×6b Memory
Yuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang,
Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan Ciena, Ottawa, Canada Modern optical systems increasingly rely on DSP techniques for data transm
ISSCC 2011 Session 11 Memory
A 151mm2 64Gb MLC NAND Flash Memory in 24nm CMOS Technology
Koichi Fukuda1, Yoshihisa Watanabe1, Eiichi Makino1, Koichi Kawakami1,
Junpei Sato1, Teruo Takagiwa1, Naoaki Kanagawa1, Hitoshi Shiga1, Naoya Tokiwa1, Yoshihiko Shindo1, Toshiaki Edahiro1, Takeshi Ogawa1, Makoto Iwai1, Osamu Nagao1, Junji Musha1, Takatoshi Minamoto1, Kosuke Yanagidaira1, Yu
ISSCC 2011 Session 11 Memory
A 4Mb Embedded SLC Resistive-RAM Macro with 7.2ns Read-Write Random-Access Time and 160ns MLC-Access Capability
Shyh-Shyuan Sheu1, Meng-Fan Chang2, Ku-Feng Lin2, Che-Wei Wu2,
Yu-Sheng Chen1,2, Pi-Feng Chiu1,2, Chia-Chen Kuo2, Yih-Shan Yang2, Pei-Chia Chiang1, Wen-Pin Lin1, Che-He Lin1, Heng-Yuan Lee1, Pei-Yi Gu1, Sum-Min Wang1, Frederick T. Chen1, Keng-Li Su1, Chen-Hsin Lien2, Kuo-Hsing Cheng
ISSCC 2011 Session 11 Memory
A 32Gb MLC NAND Flash Memory with Vth Margin-Expanding Schemes in 26nm CMOS
Tae-yun Kim, Sang-Don Lee, Jin-su Park, Ho-youb Cho,
Byoung-sung You, kwang-ho Baek, Jae-ho Lee, Chang-won Yang, Misun Yun, Min-su Kim, Jong-woo Kim, Eun-seong Jang, Hyun Chung, Sang-o Lim, Bong-Seok Han, Yo-Hwan Koh Hynix Semiconductor, Icheon, Korea As the NAND flash mem
ISSCC 2011 Session 11 Memory
95%-Lower-BER 43%-Lower-Power Intelligent SolidState Drive (SSD) with Asymmetric Coding and Stripe Pattern Elimination Algorithm
Shuhei Tanakamaru1, Chinglin Hung1, Atsushi Esumi2, Mitsuyoshi Ito2,
memory errors by 95% and reduce power consumption by 43%. Figure 11.4.1 shows the measured memory cell error in the data retention and program disturb of 4X, 3X and 2Xnm NAND flash memories. As the memory size decreases,
Kai Li2, Ken Takeuchi1 1 2 University of Tokyo, Tokyo, Japan, SIGLEAD,
ISSCC 2011 Session 11 Memory
An Offset-Tolerant Current-Sampling-Based Sense Amplifier for Sub-100nA-Cell-Current Nonvolatile Memory
Meng-Fan Chang1, Shin-Jang Shen1, Chia-Chi Liu1, Che-Wei Wu1,
Yu-Fan Lin1, Shang-Chi Wu1, Chia-En Huang1,2, Han-Chao Lai1,2, Ya-Chin King1, Chorng-Jung Lin1, Hung-Jen Liao2, Yu-Der Chih2, Hiroyuki Yamauchi3 National Tsing Hua University, Hsinchu, Taiwan, TSMC, Hsinchu, Taiwan, 3 Fu
ISSCC 2011 Session 11 Memory
A Low-Voltage 1Mb FeRAM in 0.13µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin in Scaled CMOS
Masood Qazi1, Michael Clinton2, Steven Bartling2, Anantha P. Chandrakasan1
Massachusetts Institute of Technology, Cambridge, MA, Texas Instruments, Dallas, TX 2 Low-power portable electronics such as implantable medical devices require low-access-energy non-volatile memory to deliver longer bat
ISSCC 2011 Session 11 Memory
A 4Mb Conductive-Bridge Resistive Memory with 2.3GB/s Read-Throughput and 216MB/s Program-Throughput
Wataru Otsuka1, Koji Miyata1, Makoto Kitagawa1, Keiichi Tsutsui1,
higher performance in the storage and access of data in various consumer electronic and computing devices has driven the development of nonvolatile memory (NVM) technologies. The promising candidates for future NVM such
Tomohito Tsushima1, Hiroshi Yoshihara2, Tomohiro Namise2, Yasuhiro Ter
ISSCC 2011 Session 11 Memory
A 7MB/s 64Gb 3-Bit/Cell DDR NAND Flash Memory in 20nm-Node Technology
Ki-Tae Park, Ohsuk Kwon, Sangyong Yoon, Myung-Hoon Choi,
In-Mo Kim, Bo-Geun Kim, Min-Seok Kim, Yoon-Hee Choi, Seung-Hwan Shin, Youngson Song, Joo-Yong Park, Jae-Eun Lee, Chang-Gyu Eun, Ho-Chul Lee, Hyeong-Jun Kim, Jun-Hee Lee, Jong-Young Kim, Tae-Min Kweon, Hyun-Jun Yoon, Taeh
ISSCC 2011 Session 12 Other
A 95mV-Startup Step-Up Converter with VTH-Tuned Oscillator by Fixed-Charge Programming and Capacitor Pass-On Scheme
Po-Hung Chen1, Koichi Ishida1, Katsuyuki Ikeuchi1, Xin Zhang1,
Yokohama, Japan 2 Harvesting energy from the environment by using a thermoelectric generator (TEG) or photovoltaic cells provides a solution for battery-free sensor networks or electronic healthcare systems. In these sys
Kentaro Honda1, Yasuyuki Okuma2, Yoshikatsu Ryu2, Makoto Takamiya1, Ta
ISSCC 2011 Session 12 Other
100V AC Power Meter System-on-a-Film (SoF) Integrating 20V Organic CMOS Digital and Analog Circuits with Floating Gate for Process-Variation Compensation and 100V Organic PMOS Rectifier
Koichi Ishida1, Tsung-Ching Huang1, Kentaro Honda1,
Tsuyoshi Sekitani1, Hiroyoshi Nakajima2, Hiroki Maeda2, Makoto Takamiya1, Takao Someya1, Takayasu Sakurai1 1 University of Tokyo, Tokyo, Japan, Dai Nippon Printing, Chiba, Japan 2 A smart meter is essential for realizing
ISSCC 2011 Session 12 Other
Real-Time Current-Waveform Sensor with Plugless Energy Harvesting from AC Power Lines for Home/Building Energy-Management Systems
Shingo Takahashi, Nobuhide Yoshida, Kenichi Maruhashi, Muneo Fukaishi
are expected to be key to the achievement of an upgraded energy infrastructure, such as Smart Grid. While EMS may offer monitoring, reporting, and control of energy usage, these functions simply track intermittently the
NEC, Kawasaki, Japan Home/building energy-management systems (EMSs) dr
ISSCC 2011 Session 12 Other
A 3.9ns 8.9mW 4×4 Silicon Photonic Switch Hybrid Integrated with CMOS Driver
Alexander Rylyakov, Clint Schow, Benjamin Lee, William Green,
Joris Van Campenhout, Min Yang, Fuad Doany, Solomon Assefa, Christopher Jahnes, Jeffrey Kash, Yurii Vlasov IBM T. J. Watson Reseach Center, Yorktown Heights, NY The emerging field of silicon photonics [1-3] targets monol
ISSCC 2011 Session 12 Other
A 820GHz SiGe Chipset for Terahertz Active Imaging Applications
Erik Öjefors1, Janus Grzyb1, Yan Zhao1, Bernd Heinemann2,
mmWave imaging systems can be improved by an increase of their operating frequencies into the submillimeterwave range (300GHz to 3THz). Electronic terahertz sources and receivers are presently dominated by III/V semicond
Bernd Tillack2, Ullrich R Pfeiffer1 1 University of Wuppertal, Wuppert
ISSCC 2011 Session 12 Other
A 130µA Wake-Up Receiver SoC in 0.13µm CMOS for Reducing Standby Power of An Electric Appliance Controlled by An Infrared Remote Controller
Hiroaki Ishihara1, Toshiyuki Umeda1, Katsuya Ohno2, Shigeyasu Iwata2,
zero emissions of carbon dioxide, wake-up circuits have attracted attention as a promising approach for reducing standby power [1]. The dominant consumers of standby power are household electric appliances driven by AC p
Fumi Moritsuka1, Tetsuro Itakura1, Manabu Ishibe2, Keijiro Hijikata2,
ISSCC 2011 Session 12 Other
Programmable Cell Array Using Rewritable SolidElectrolyte Switch Integrated in 90nm CMOS
Makoto Miyamura1, Shogo Nakaya2, Munehiro Tada1,
Toshitsugu Sakamoto1, Koichiro Okamoto1, Naoki Banno1, Shinji Ishida1, Kimihiko Ito1, Hiromitsu Hada1, Noboru Sakimura1, Tadahiko Sugibayashi1, Masato Motomura2 1 NEC, Sagamihara, Japan, NEC, Kawasaki, Japan 2 Programmab
ISSCC 2011 Session 12 Other
6W/25mm2 Inductive Power Transfer for Non-Contact Wafer-Level Testing
Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura,
nonfunctional devices early in the fabrication process. It is commonly performed by placing a probe card directly above a device under test (DUT) and establishing a mechanical contact between them by means of an array of
Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda Keio University, Yok
ISSCC 2011 Session 12 Other
GHz-Range Continuous-Time Programmable Digital FIR with Power Dissipation that Automatically Adapts to Signal Activity
Mariya Kurchuk1, Colin Weltin-Wu1, Dominique Morche2, Yannis Tsividis1
2 Columbia University, New York, NY, CEA-LETI-MINATEC, Grenoble, France GHz-range applications that operate in a variety of signal situations and/or multiple standards require highly programmable responses that cannot be
ISSCC 2011 Session 13 Analog Circuits
A Simple LED Lamp Driver IC with Intelligent Power-Factor Correction
Jong Tae Hwang, Kunhee Cho, Donghwan Kim, Minho Jung,
lighting devices [1, 2] and LCD backlight devices [3]. Prior to emergence of highperformance LED devices, the fluorescent lamps have been in a strong position in lighting systems as compared to the incandescent lamps sin
Gyehyun Cho, Seunguk Yang Fairchild Semiconductor, Bucheon, Korea High
ISSCC 2011 Session 13 Analog Circuits
A 1.2A Buck-Boost LED Driver with 13% Efficiency Improvement Using Error-Averaged SenseFET-Based Current Sensing
Sachin Rao1, Qadeer Khan1, Sarvesh Bang2, Damian Swank2,
significant efficiency loss due to the presence of a current regulation element (CRE) in series with the LED. In a conventional driver, either a series current source [1] or a sense resistor [2, 3] acts as a CRE to regul
Arun Rao2, William McIntyre2, Pavan Kumar Hanumolu1 1 2 Oregon State U
ISSCC 2011 Session 13 Analog Circuits
Filterless Integrated Class-D Audio Amplifier Achieving 0.0012% THD+N and 96dB PSRR When Supplying 1.2W
Mykhaylo Teplechuk, Tony Gribben, Christophe Amadi
Dialog Semiconductor, Edinburgh, United Kingdom High power efficiency, small size and reduced heat dissipation are highly desirable in battery-powered mobile systems and switched-mode class-D amplifiers can readily satis
ISSCC 2011 Session 13 Analog Circuits
A 5.9nV/√Hz Chopper Operational Amplifier with 0.78µV Maximum Offset and 28.3nV/°C Offset Drift Yoshinori Kusuda
Analog Devices, Wilmington, MA, Many auto-zero or chopper operational amplifiers have been reported with low
offset and low-offset drift. The resulting baseband noise can also be a significant error source, and thus reducing the total error down to sub µV levels at DC and low frequencies has been targeted. Chopping is more suit
ISSCC 2011 Session 13 Analog Circuits
A Current-Feedback Instrumentation Amplifier with a Gain Error Reduction Loop and 0.06% Untrimmed Gain Error
Rong Wu, Johan H. Huijsing, Kofi A.A. Makinwa
Current-feedback instrumentation amplifiers (CFIAs) have significant advantages over the classic three-opamp topology: better power efficiency [1, 2], higher CMRR and rail-sensing capability [4]. Their main disadvantage,
Delft University of Technology, Delft, The Netherlands
ISSCC 2011 Session 13 Analog Circuits
A 6.7nV/√Hz Sub-mHz-1/f-Corner 14b Analog-toDigital Interface for Rail-to-Rail Precision Voltage Sensing
Chinwuba D. Ezekwe, Johan P. Vanderhaegen, Xinyu Xing, Ganesh K. Balachandran
Robert Bosch, Palo Alto, CA Many sensors demand energy-efficient precision voltage sensing interfaces with low noise performance down to very low frequencies. Examples include micro Kelvin resolution temperature sensors
ISSCC 2011 Session 13 Analog Circuits
A 36V JFET-Input Bipolar Operational Amplifier with 1µV/°C Maximum Offset Drift and –126dB Total Harmonic Distortion
Martijn F. Snoeij, Mikhail V. Ivanov
A 36V JFET-input bipolar operational amplifier is presented with a maximum offset drift of 1µV/°C over a temperature range of –40 to 125°C, which represents a 3x improvement on the state-of-the-art. This is achieved with
Texas Instruments, Erlangen, Germany
ISSCC 2011 Session 13 Analog Circuits
A 3.3V-Supply 120mW Differential ADC Driver Amplifier in 0.18µm SiGe BiCMOS with 108dBc IM3 at 100MHz Gwilym F. Luff
Intersil, Harlow, United Kingdom, Fully differential (operational) amplifiers (FDA) have become the preferred
method of driving 1st and 2nd Nyquist zone signals into 100 to 500 Ms/s 12 to 16 bit ADCs. Previously the best performance (95dBc IM3 at 100MHz [1]) came from designs in dielectrically isolated (DI) Silicon Germanium com
ISSCC 2011 Session 14 Memory
A 64Mb SRAM in 32nm High-k Metal-Gate SOI
Technology with 0.7V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements
Harold Pilo1, Igor Arsovski1, Kevin Batson1, Geordie Braceras1, John Gabric1, Robert Houle1, Steve Lamphier1, Frank Pavlik1, Adnan Seferagic1, Liang-Yu Chen2, Shang-Bin Ko2, Carl Radens2 1 IBM Systems and Technology Grou
ISSCC 2011 Session 14 Memory
A 4R2W Register File for a 2.3GHz Wire-Speed POWERTM Processor with Double-Pumped Write Operation
Gary S. Ditlow1, Robert K. Montoye1, Salvatore N. Storino2,
Sherman M. Dance2, Sebastian Ehrenreich3, Bruce M. Fleischer1, Thomas W. Fox1, Kyle M. Holmes4, Junichi Mihara5, Yutaka Nakamura5, Shohji Onishi5, Robert Shearer2, Dieter Wendel6, Leland Chang1 1 IBM T. J. Watson Reseach
ISSCC 2011 Session 14 Memory
An 8MB Level-3 Cache in 32nm SOI with ColumnSelect Aliasing
Don Weiss1, Michael Dreesen1, Michael Ciraula1, Carson Henrion1,
Chris Helt1, Ryan Freese1, Tommy Miles1, Anita Karegar1, Russell Schreiber2, Bryan Schneller1, John Wuu1 1 AMD, Fort Collins, CO, AMD, Austin, TX 2 High-performance multi-core processors require efficient multi-level cac
ISSCC 2011 Session 14 Memory
A 28nm High-Density 6T SRAM with Optimized Peripheral-Assist Circuits for Operation Down to 0.6V
Mahmut E. Sinangil1, Hugh Mair2, Anantha P. Chandrakasan1, 1
Massachusetts Institute of Technology, Cambridge, MA, Texas Instruments, Dallas, TX An increasing amount of embedded memory is used in today’s ICs and consequently the design of low-power, high-density SRAM is becoming c
ISSCC 2011 Session 15 Digital Processors
An 80Gb/s Dependable Communication SoC with PCI Express I/F and 8 CPUs ports realizes a high performance communication link with a theoretical peak bandwidth of 4×20Gb/s.
Sugako Otani1, Hiroyuki Kondo1, Itaru Nonomura2, Atsuyuki Ikeya2,
Minoru Uemura2, Yasushi Hayakawa1, Takeshi Oshita1, Satoshi Kaneko1, Katsushi Asahina2, Kazutami Arimoto1, Shin’ichi Miura3, Toshihiro Hanawa3, Taisuke Boku3, Mitsuhisa Sato3 Figure 15.2.4 shows the PCIe PHY analog block
ISSCC 2011 Session 15 Digital Processors
A Fully-Integrated 3-Level DC/DC Converter for Nanosecond-Scale DVS with Fast Shunt Regulation
Wonyoung Kim, David M Brooks, Gu-Yeon Wei
In recent years, chip multiprocessor architectures have emerged to scale performance while staying within tight power constraints. This trend motivates percore/block dynamic voltage and frequency scaling (DVFS) with fast
Harvard University, Cambridge, MA
ISSCC 2011 Session 15 Digital Processors
A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices
Srinivasa Rao Gutta1, Denis Foley2, Ajay Naini1, Robert Wasmuth3, Don Cherepacha4
AMD, Hyderabad, India, AMD, Boxborough, MA, 3 AMD, Austin, TX, 4 AMD, Markham, Canada 2 AMD’s first Fusion Accelerated Processor Unit (APU) codenamed “Zacate” (Fig. 15.4.1) combines a pair of x86 CPUs cores codenamed “Bo
ISSCC 2011 Session 15 Digital Processors
A Programmable Adaptive Phase-Shifting PLL for Clock Data Compensation Under Resonant Supply Noise
Dong Jiao, Chris H. Kim
Power supply noise has become one of the main performance-limiting factors in sub-1V technologies. Resonant supply noise caused by the package/bonding inductance and on-die capacitance has been reported as the dominant s
University of Minnesota, Minneapolis, MN
ISSCC 2011 Session 15 Digital Processors
A Side-Channel and Fault-Attack Resistant AES Circuit Working on Duplicated Complemented Values
Marion Doulcier-Verdier1,2, Jean-Max Dutertre2, Jacques Fournier1,2,
Cryptographic circuits can be subjected to several kinds of side-channel and fault attacks in order to extract the secret key. Side-channel attacks can be carried by measuring either the power consumed or the EM waves em
Jean-Baptiste Rigaud2, Bruno Robisson1,2, Assia Tria1,2 1 2 CEA-LETI-M
ISSCC 2011 Session 16 mm-Wave
A 21.7-to-27.8GHz 2.6-Degrees-rms 40mW Frequency Synthesizer in 45nm CMOS for mm-Wave Communication Applications
Juan F. Osorio1, Cicero S. Vaucher1, Bill Huff2, Edwin v.d. Heijden1, Anton de Graauw1
2 NXP Semiconductors, Eindhoven, The Netherlands, NXP Semiconductors, San Diego, CA This work presents a 21.7-to-27.8GHz frequency synthesizer in a 45nm CMOS process that combines a tuning range of 24.8%, a residual phas
ISSCC 2011 Session 16 mm-Wave
183GHz 13.5mW/Pixel CMOS Regenerative Receiver for mm-Wave Imaging Applications
Adrian Tang, Mau-Chung Frank Chang
Terahertz- and mm-Wave-based imagers have recently gained interest for imaging in security screening and bio-imaging applications [1,2]. For these applications to become practical, the core pixel circuits employed in an
University of California, Los Angeles, CA
ISSCC 2011 Session 16 mm-Wave
A mm-Wave Quadrature VCO Based on Magnetically Coupled Resonators
Ugo Decanis1, Andrea Ghilioni1, Enrico Monaco2,3, Andrea Mazzanti1,
University of Pavia, Pavia, Italy, 2 University of Modena e Reggio Emilia, Modena, Italy, 3 Istituto Universitario di Studi Superiori di Pavia, Pavia, Italy Wireless signal processing at mm-Waves would benefit from the a
Francesco Svelto1
ISSCC 2011 Session 16 mm-Wave
A 6.5mW Inductorless CMOS Frequency Divider-by-4 Operating up to 70GHz
Andrea Ghilioni1, Ugo Decanis1, Enrico Monaco2,3, Andrea Mazzanti1,
University of Pavia, Pavia, Italy, University of Modena e Reggio Emilia, Modena, Italy, 3 Istituto Universitario di Studi Superiori di Pavia, Pavia, Italy 2 With a cut-off frequency in excess of 250GHz, nanometer-scale C
Francesco Svelto1