A Flip-Chip-Packaged 1.8V 28dBm Class-AB Power Amplifier with Shielded Concentric Transformers in 32nm SoC CMOS

📋 论文概要

该论文提出了一种采用屏蔽同心变压器的倒装芯片封装1.8V 28dBm AB类功率放大器，解决了32nm SoC CMOS工艺中低击穿电压、高衬底损耗和封装约束导致的线性高功率放大器实现难题。

💡 主要创新点

• 提出屏蔽同心变压器结构，有效降低衬底损耗并提高功率合成效率
• 采用1.8V低电源电压实现28dBm高输出功率，克服了先进CMOS工艺的低击穿电压限制
• 针对倒装芯片封装优化设计，满足严格的凸点图案约束和散热要求

🏷 关键词

📄 原文摘要

Intel, Hillsboro, OR As CMOS technology continues to scale for SoC applications, significant challenges to implement a monolithic linear high-power amplifier have emerged. This results from the low breakdown voltage of transistors, high on-chip passive loss on a conductive substrate, stringent bump-pattern constraints and thermal dissipation requirements of flip-chip packages. Most fully-integrated linear CMOS PAs reported to date were either fabricated on a relatively mature process (65nm or above) in a wire-bonded die with relatively high supply voltage (3.3V) [1-3], or exhibited low power efficiency when backed-off. In many cases, digital pre-distortion was implemented to improve linearity and efficiency [2,3]. We present a 1.8V single-chip CMOS PA with 21dBm average output power and 16% PAE while meeting -25dB EVM for 64-QAM OFDM signal without digital pre-distortion linearization in 32nm SoC CMOS on a flip-chip package. This performance is enabled by: 1) On-chip shielded concentri

👥 作者与机构

Yulin Tan, Hongtao Xu, Mohammed A El-tanani, Stewart Taylor, Hasnain Lakdawala