A 77% Energy-Saving 22-Transistor Single-PhaseClocking D-Flip-Flop with Adaptive-Coupling Configuration in 40nm CMOS

📋 论文概要

该论文提出了一种自适应耦合触发器（ACFF），通过减少晶体管数量并采用单相时钟技术，在40nm CMOS工艺中实现了77%的能耗节省，解决了传统触发器因内部节点冗余翻转导致的高功耗问题。

💡 主要创新点

• 提出自适应耦合配置，通过减少内部节点冗余翻转来降低功耗，同时仅使用22个晶体管，比现有低功耗触发器更小。
• 采用单相时钟方案，简化时钟分布网络，进一步降低动态功耗。

🏷 关键词

📄 原文摘要

Flip-flops (FF) typically consume more than 50% of random-logic power in an SoC chip, due to their redundant transition of internal nodes, when the input and the output are in the same state. Several low-power techniques have been proposed [1-5], but all of them incur transistor-count penalties, leading to an increase in size, which is too costly since flip-flops typically account for 50% of random-logic area. In this work, we design and test a D-flip-flop, known as adaptive-coupling flip-flop (ACFF), which has a reduced transistor count compared to other low-power flip-flops, and 2 fewer transistors than the mainstream transmission-gate flip-flop (TGFF). ACFF features a single-phase clocking structure, with no local clock buffer and no precharging stage, enabling it to be more energy efficient than TGFF, where up to 77% energy saving is achieved at 0% data activity. ACFF also has an adaptive-coupling configuration, which weakens stateretention coupling during a transition, allowing it

👥 作者与机构

Chen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada

Toshiba, Kawasaki, Japan