An 800MS/s Dual-Residue Pipeline ADC in 40nm CMOS

📋 论文概要

本文提出了一种采用双残差架构的800MS/s 12位流水线ADC，在40nm CMOS工艺下实现了59dB峰值SNDR和105mW功耗，FOM为0.18pJ/转换步。该架构仅需校准MDAC放大器的失调电压，简化了校准算法。

💡 主要创新点

• 采用双残差（dual-residue）流水线架构，仅需校准MDAC放大器的失调电压，大幅降低校准复杂度。
• 在40nm CMOS工艺下实现800MS/s采样率，同时保持0.18pJ/转换步的高能效。

🏷 关键词

📄 原文摘要

Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult Broadcom, Bunnik, The Netherlands The 800MS/s 12b pipeline ADC presented here achieves a 59dB peak SNDR while consuming 105mW, resulting in an FOM of 0.18pJ/conversion-step. With digital power dissipation decreasing with technology much faster than analog power consumption, power efficient ADC designs have to make use of calibration. A major advantage offered by the dual-residue ADC architecture [1] is that the only calibration required is a calibration of the offset voltages of the MDAC amplifiers; a simple algorithm has been implemented that reaches convergence very rapidly and tracks the offsets for temperature drift and aging. Furthermore, the relaxed open-loop gain and bandwidth requirements of the MDACs allowed for a low-power implementation. Low power consumption is essential especially in applications where multiple high-speed ADCs have to be implemented on a

👥 作者与机构

Jan Mulder, Frank M.L. van der Goes, Davide Vecchi, Jan R. Westra,