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ISSCC 2011Session 25 · CDRs & EQUALIZATION TECHNIQUESWireline I/O

A 13.8mW 3.0Gb/s Clock-Embedded Video Interface with DLL-Based Data-Recovery Circuit

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📋 论文概要

该论文提出了一种基于DLL的数据恢复电路的时钟嵌入视频接口,实现了13.8mW功耗和3.0Gb/s的数据速率,解决了传统多点配置接口在高带宽下成本高的问题。

💡 主要创新点

核心指标
13.8mW功耗,3.0Gb/s数据速率
重要性
发表年份
ISSCC 2011

🏷 关键词

时钟嵌入DLL数据恢复电路视频接口低功耗

📄 原文摘要

As the panel technology continues to offer displays with higher resolution, greater color depth, and increased frame rate, the amount of video data to display driver ICs (DDIs) inside the panel keeps on expanding. Since the conventional intra-panel interfaces with multi-drop configurations, such as RSDS and mini-LVDS, increase the cost of overall systems at high bandwidth, new intrapanel interfaces have been proposed to meet the bandwidth requirement with point-to-point configurations [1-5]. This paper presents a new high-speed video interface that offers significant complexity reduction in the receiver. It is because receivers are integrated in a DDI with relatively slow high-voltage processes, while transmitters in host controllers are implemented with the more advanced deep-submicron processes. Compared to the PLL-based clock recovery circuits in [1-2], the DLL-based data recovery circuit occupies a smaller area with lower

👥 作者与机构

Sungchun Jang, Heesoo Song, Seokmin Ye, Deog-Kyoon Jeong

Seoul National University, Seoul, Korea

分类:Wireline I/O · 年份:ISSCC 2011