Dynamic Hit Logic with Embedded 8Kb SRAM in 45nm SOI for the zEnterpriseTM Processor

📋 论文概要

该论文提出了一种14位动态命中逻辑方案，并集成了8Kb SRAM，用于zEnterpriseTM处理器的L1缓存查找结构。通过采用“搜索命中”方案（XOR后接AND功能，预充电为未命中）优化了性能、时序和功耗，并利用可编程ABIST引擎实现了SRAM和命中逻辑的联合测试。

💡 主要创新点

• 提出动态命中逻辑与嵌入式SRAM的集成方案，通过预充电为未命中的XOR-AND结构实现快速查找。
• 采用自定义微码可编程ABIST引擎，实现SRAM和命中逻辑的联合“全速”测试，确保电路功能和时序裕量。

🏷 关键词

📄 原文摘要

logic functions are making their way onto critical path SRAMs in the L1 cache look up structure. Described in this paper is a 14 bit dynamic hit logic scheme with an embedded 8K bit SRAM in IBM’s 45nm SOI [3]. The hit logic uses a “search-for-a-hit” scheme (i.e., XOR’s followed by AND functions, pre-charged to a miss) to provide optimal performance, timing, and power. A custom microcode programmable Array-BuiltIn-Self-Test (ABIST) engine tests both the SRAM and hit logic function jointly, resulting in comprehensive “at-speed” test coverage to guarantee circuit functionality and timing margins. The SRAM is organized as a 64×15b×8W (way, or set) array and uses a 6T SRAM cell (1Read/1Write, 0.462µm2) in a “domino” hierarchal dual read bitline approach [1] In the Load/Store Unit (LSU) of the zEnterprise 196 microprocessor core, this hit

👥 作者与机构

Antonio R Pelella, Yuen H Chan, Bargav Balakrishnan, Pradip Patel,

Daniel Rodko, Richard E Serton IBM Systems and Technology Group, Poughkeepsie, NY With the push to ever higher core frequencies, more