A 1-to-6Gb/s Phase-Interpolator-Based Burst-Mode CDR in 65nm CMOS

📋 论文概要

这篇论文提出了一种基于相位插值器的突发模式时钟数据恢复(CDR)电路，工作速率范围为1-6Gb/s，采用65nm CMOS工艺。它解决了在无源光网络(PON)等应用中需要快速锁定(数十个UI内)的问题，相较于传统的注入锁定或门控VCO方法，提供了新的实现方案。

💡 主要创新点

• 采用相位插值器代替传统的注入锁定或门控VCO，实现快速锁定和宽速率范围的突发模式CDR。
• 支持1至6Gb/s的宽数据速率范围，适用于多种PON标准。

🏷 关键词

📄 原文摘要

are widely used in passive optical networks (PON) [1] and as a replacement for conventional CDRs in clock-forwarding links to reduce power [2]. In PON, a single CDR performs the task of clock and data recovery for several burst sequences, each originating from a different source. As a result, the BMCDR is required to lock to an incoming data stream within tens of UIs (for example 40ns in GPON). Previous works use either injection locking [3, 4] or gated VCO [5, 6] to achieve this fast locking. In both cases, the control voltage of the CDR’s VCO is generated by a reference PLL with a matching VCO to guarantee accurate frequency locking. However, any component mismatch between the two VCO’s results in a frequency offset between the reference PLL frequency and the CDR’s VCO frequency,

👥 作者与机构

Behrooz Abiri1, Ravi Shivnaraine1, Ali Sheikholeslami1,

Hirotaka Tamura2, Masaya Kibune2 1 2 University of Toronto, Toronto, Canada Fujitsu Laboratories, Kawasaki, Japan Burst-mode clock and data recovery circuits (BMCDR)