A 62mV 0.13µm CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic

📋 论文概要

该论文提出了一种基于施密特触发逻辑的标准单元设计技术，能够在0.13µm CMOS工艺下实现62mV的超低电压工作。通过利用施密特触发器的滞回特性，解决了亚阈值电路中因工艺变化导致的逻辑门失效问题，从而在极低电源电压下实现可靠的数字逻辑操作。

💡 主要创新点

• 提出使用施密特触发逻辑替代传统CMOS逻辑，利用其滞回特性增强噪声容限，使电路能在62mV的极低电压下稳定工作。
• 开发了基于标准单元的设计流程，将施密特触发逻辑集成到标准单元库中，便于自动化综合和布局布线。
• 通过实验验证了该技术在0.13µm CMOS工艺下的可行性，展示了在超低电压下实现复杂数字电路的能力。

🏷 关键词

📄 原文摘要

University of Freiburg - IMTEK, Freiburg, Germany, HSG-IMIT, Villingen-Schwenningen, Germany Sub-threshold circuits have recently gained attention mainly due to the possibility of operating at the minimum energy per operation point [1]. There are applications where a supply voltage reduction below this point is advantageous though, even at the cost of increasing active energy per operation. Always-on circuits, e.g. wake-up circuitry for chips sleeping at ultra-low supply voltages, reduce power consumption with decreasing supply. Furthermore, energy-harvesting applications are often limited by the very low output voltages of the harvesting devices, thus the minimum VDD of the electronic circuits dictates when active operation can start (e.g. thermoelectric harvesters [2]). Numerous ultra-low-voltage circuits have been demonstrated: A 180mV FFT processor is shown in [1] and a SRAM cell applying feed-forward of inverter

👥 作者与机构

Niklas Lotze1,2, Yiannos Manoli1,2, 1