⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一种基于电流采样的容忍偏移读出放大器，用于亚100nA单元电流的非易失性存储器。通过AC耦合实现电流比放大，有效解决了低电流下读出放大器的偏移问题，提高了读操作可靠性。
Yu-Fan Lin1, Shang-Chi Wu1, Chia-En Huang1,2, Han-Chao Lai1,2, Ya-Chin King1, Chorng-Jung Lin1, Hung-Jen Liao2, Yu-Der Chih2, Hiroyuki Yamauchi3 National Tsing Hua University, Hsinchu, Taiwan, TSMC, Hsinchu, Taiwan, 3 Fukuoka Institute of Technology, Fukuoka, Japan At the beginning of phase-2, the M1/M2 charges the SA1/SA2 with the current sampled at phase-1. For a given TP2 period, M1/M2 raises the VSA1/VSA2 by the amount of ΔVSA1/ΔVSA2. Due to AC-coupling behavior of C1/C2, the ΔVSA1 reduces the VG2 and ΔVSA2 reduces the VG1. This results in an amplification of the current ratio (CR=IM2/IM1) or current difference (ΔIM1-M2=IM1-IM2) between M1 and M2. This CR-amplification speeds up the development of difference (ΔVSA) between VSA1 and VSA2. In phase-3 (2nd-stage amplifying), the EN turns on the NMOS-latch and pulls down the SA2 while M1 continually charges the SA1 to VDD. Finally, the digital output is generated at node SA1 and SA2.
Meng-Fan Chang1, Shin-Jang Shen1, Chia-Chi Liu1, Che-Wei Wu1,