A Direct Digital Frequency Synthesizer with Minimized Tuning Latency of 12ns

📋 论文概要

该论文提出了一种具有最小化调谐延迟的直接数字频率合成器（DDS），通过优化相位累加器（PA）的进位传播问题，实现了12ns的调谐延迟。解决了传统DDS中长进位链导致的瓶颈，同时避免了流水线化带来的延迟增加。

💡 主要创新点

• 提出了一种新型相位累加器架构，通过减少进位传播路径来降低调谐延迟。
• 在保持高数据速率的同时，实现了12ns的最小化调谐延迟，优于传统流水线方法。

🏷 关键词

📄 原文摘要

A downside for all direct digital synthesizer (DDS) architectures is that every DDS has a phase accumulator (PA) whose normalized phase value φ must be updated for each (sin 2πφ, cos 2πφ) output-pair produced, and such updating introduces a rather long carry-ripple. PA lengths of 32-b are commonplace and 48-b or longer PA can be found in commercial DDS products. When a DDS with high data-rate is needed, the long PA carry-ripple can present a serious bottleneck—one usually overcome by some form of PA pipelining—but then, only at the cost of a significant increase in “tuning latency” as well as added power consumption and chip-area. Ref. [1] explains how (for a mere 24-b PA) such pipelining introduces a 55-cycle latency, setting the system’s frequency-hopping limit at 700/55 = 12.7MHz, for a DDS generating outputs at 700MHz. All such PA pipelining difficulties are completely eliminated by the architecture reported

👥 作者与机构

Alan Willson, Mukund Ojha, Shilpa Agarwal, Thriven Lai, Tzu-chieh Kuo

University of California, Los Angeles, CA