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该论文提出了一种高度并行且可扩展的CABAC解码器，用于下一代视频编码标准HEVC，解决了高分辨率（如QFHD）和高帧率（如120fps）下的解码吞吐量瓶颈，同时通过并行架构降低了功耗，适用于便携设备。
Future video decoders will need to support high resolutions such as Quad Full HD (QFHD, 4096×2160) and fast frame rates (e.g. 120fps). Many of these decoders will also reside in portable devices. The next-generation standard called High-Efficiency Video Coding (HEVC), which is being developed as a successor to H.264/AVC, not only seeks to improve the coding efficiency but also to account for implementation complexity and leverage parallelism to meet future power and performance demands [1]. Parallel processing increases the throughput for higher performance, which can be traded-off for lower power with voltage scaling. This paper presents a silicon prototype for a pre-standard algorithm developed for HEVC (“H.265”) called Massively Parallel CABAC (MPCABAC) that addresses a key video decoder bottleneck. The test chip has over an order-of-magnitude higher throughput than state-of-the-art H.264/AVC
Vivienne Sze, Anantha P. Chandrakasan
Massachusetts Institute of Technology, Cambridge, MA