A 0.1-fref BW 1GHz Fractional-N PLL with FIREmbedded Phase-Interpolator-Based Noise Filtering

📋 论文概要

该论文提出了一种基于FIRE嵌入相位插值器噪声滤波的分数N锁相环，通过创新的噪声滤波技术有效降低了ΔΣ量化噪声，解决了传统设计中环路带宽受限于带内VCO噪声与ΔΣ量化噪声之间权衡的问题。

💡 主要创新点

• 提出FIRE嵌入相位插值器结构，实现高效的噪声滤波，无需额外功耗和面积。
• 采用分数相位旋转技术替代传统双模分频器，进一步降低ΔΣ量化噪声。

🏷 关键词

📄 原文摘要

In the design of a fractional-N PLL, the trade-off between in-band VCO noise and ΔΣ quantization noise constrains the choice of loop bandwidth. Various circuit schemes have been proposed to relax such constrains with noise canceling methods [1, 2] at the cost of significant extra power and chip area, and with FIR filtering techniques [3, 4] utilizing multiple charge pumps (CPs), PFDs and dividers. To reduce the ΔΣ quantization noise, fractional phase rotation [4] has been also a popular approach as an alternative to the dual modulus divider. However, high-resolution phase interpolators (PIs) suffer from nonlinearities due to random mismatches among phase steps and systematic imperfections in circuit operation when the interpolated vector approaches quadrant boundaries, and such nonlinearities eventually limit the amount of noise reduction in PIbased PLL. This work presents a 1GHz ΔΣ fractional-N PLL based on the noise

👥 作者与机构

Dong-Woo Jee, Yunjae Suh, Hong-June Park, Jae-Yoon Sim

Pohang University of Science and Technology, Pohang, Korea