A 2.9-to-4.0GHz Fractional-N Digital PLL with BangBang Phase Detector and 560fsrms Integrated Jitter at 4.5mW Power

📋 论文概要

本文提出了一种基于1位时间数字转换器（即bang-bang相位检测器）的分数-N数字锁相环，在4.5mW功耗下实现了560fsrms的积分抖动（3kHz至30MHz），解决了传统高性能TDC设计复杂且功耗大的问题。

💡 主要创新点

• 采用1位TDC（bang-bang相位检测器）替代高分辨率TDC，大幅简化了数字PLL的设计并降低了功耗。
• 在分数-N数字PLL中实现了优异的抖动-功耗折中，达到了560fsrms抖动@4.5mW的性能。

🏷 关键词

📄 原文摘要

Carlo Samori, Andrea L. Lacaita Politecnico di Milano, Milan, Italy State-of-the-art digital fractional-N PLLs intended for modern wireless systems make use of high-resolution and high-linearity time-to-digital converters (TDCs) in order to meet the stringent integral phase noise requirements [1, 2]. Those high-performance TDCs complicate the synthesizer design and dissipate large part of the power budget, leading to poor jitter-power compromise. This paper introduces a fractional-N PLL based on a 1b TDC, achieving jitter of 560fsrms (from 3kHz to 30MHz) at 4.5mW power consumption, even in the worst-case of fractional spur falling within the PLL bandwidth. The circuit synthesizes frequencies between 2.92 and 4.05GHz with 70Hz resolution. Figure 5.1.1 shows the PLL block diagram, where the standard-cell-based digital blocks are filled in gray. The TDC is a single D-flip-flop, which in the following will be referred to as the bang-bang phase detector (PD). Bang-bang PDs are

👥 作者与机构

Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino,