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本文在32nm高k金属栅极SOI工艺上实现了一款64Mb SRAM宏单元，位单元面积仅0.154µm²，相比45nm设计缩小2倍。通过稳定性、写入能力和读取能力的优化，实现了0.7V的低压工作。
Harold Pilo1, Igor Arsovski1, Kevin Batson1, Geordie Braceras1, John Gabric1, Robert Houle1, Steve Lamphier1, Frank Pavlik1, Adnan Seferagic1, Liang-Yu Chen2, Shang-Bin Ko2, Carl Radens2 1 IBM Systems and Technology Group, Essex Junction, VT, IBM Systems and Technology Group, Hopewell Junction, NY 2 A 64Mb SRAM macro is fabricated in a 32nm high-k metal-gate (HKMG) SOI technology [1]. Figure 14.1.1 shows the 0.154µm2 bitcell (BC). A 2× size reduction from the previous 45nm design [2] is enabled by an equal 2× reduction in BC area. No corner rounding of BC gates allows tighter overlay of gate electrode and active area. The introduction of HKMG provides a significant reduction in the equivalent oxide thickness, thereby reducing the Vt mismatch. This reduction allows aggressive scaling of device dimensions needed to achieve the small area footprint. A 0.7V VDDMIN operation is enabled by three assist features. Stability
Technology with 0.7V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements