A Highly Digital 0.5-to-4Gb/s 1.9mW/Gb/s SerialLink Transceiver Using Current-Recycling in 90nm CMOS

📋 论文概要

该论文提出了一种采用电流回收技术的高度数字化串行链路收发器，在90nm CMOS工艺下实现0.5至4Gb/s的数据速率和1.9mW/Gb/s的能效。通过使用两个固定电压而非自适应电源调节，消除了对高效率DC-DC转换器的需求，从而提升了功率效率。

💡 主要创新点

• 采用电流回收技术，将发射器和接收器的电流复用，降低总功耗。
• 完全数字化的架构，避免低电压下模拟电路的设计难题，并利用两个固定电压工作，无需复杂电源管理。

🏷 关键词

📄 原文摘要

bandwidth in high performance compute systems is driving the need for energy-efficient multi-Gb/s I/O serial links. Improved power efficiency was demonstrated using adaptive supply regulation [1, 2]. However, power losses in the DC-DC converter needed to generate the optimal supply voltage and the difficulty in operating analog circuits at low voltages limit the power savings. Instead of scaling the supply with the data rate, we seek to operate with two fixed voltages and eliminate the need for a high-efficiency DC-DC converter. To this end, this paper presents a serial link using a highly efficient current recycling-based implicit DC-DC conversion to generate 0.6V from a 1.2V supply. Highly digital clocking circuits capable of operating at

👥 作者与机构

Rajesh Inti1, Amr Elshazly1, Brian Young1, Wenjing Yin1, Marcel Kossel2,

Thomas Toifl2, Pavan Kumar Hanumolu1 1 Oregon State University, Corvallis, OR 2 IBM Zurich Research Laboratory, Zurich, Switzerland Ever-growing demand for higher communication