A GPS/Galileo SoC with Adaptive In-Band Blocker Cancellation in 65nm CMOS

📋 论文概要

该论文提出了一款65nm CMOS工艺的GPS/Galileo SoC，通过自适应带内阻塞消除技术解决了传统方案需要多个SAW滤波器的问题，实现了低功耗和小型化，适合与蜂窝、蓝牙、WLAN等射频系统共存。

💡 主要创新点

• 提出了自适应带内阻塞消除技术，无需外部SAW滤波器即可抑制强干扰。
• 实现了单芯片GPS/Galileo SoC集成，降低了功耗和面积。
• 采用65nm CMOS工艺，满足手持设备对低功耗和小尺寸的需求。

🏷 关键词

📄 原文摘要

Kuan-I Li1, Jui-Lin Hsu1, Chi-Lun Lo1, Hsin-Hua Chen1, Sheng-Yuan Su1, Kun-Tso Chen1, Min Chen1, Osama Shana’a2, Shu-Hung Chou1, George Chien3 1 3 MediaTek, Hsinchu, Taiwan, 2MediaTek, Singapore, Singapore, MediaTek, San Jose, CA The proliferation of location-based applications inside various handheld electronic devices, such as mobile phones and internet tablets, demands the GPS system to have low power consumption, small form-factor and be co-located on the same device with other radio systems, such as cellular, BT, and WLAN. The conventional GPS solution often uses two SAW filters, before and after an external LNA, to meet the requirements of low noise and multi-radio coexistence. Nevertheless, it is highly desirable to remove the external LNA and interstage SAW filter due to size and cost, which presents a great design challenge to achieve high out-of-band linearity with very low power consumption. To fulfill

👥 作者与机构

Chia-Hsin Wu1, Wen-Chieh Tsai1, Chun-Geik Tan2, Chun-Nan Chen1,