Programmable Cell Array Using Rewritable SolidElectrolyte Switch Integrated in 90nm CMOS

📋 论文概要

该论文提出了一种使用可重写固态电解质开关的可编程单元阵列，并将其集成在90nm CMOS工艺中，旨在解决基于SRAM的FPGA因待机漏电流和阈值电压变化导致的功耗和面积挑战。通过后道工序器件集成，缩小了FPGA与基于单元ASIC之间的性能差距。

💡 主要创新点

• 采用可重写固态电解质开关替代传统SRAM存储单元，降低了待机漏电流和电路面积。
• 将固态电解质开关作为后道工序器件集成在90nm CMOS互连层中，实现了高密度可编程互连。
• 提出了基于新型开关的可编程单元阵列架构，支持重复编程并改善了FPGA的性能与功耗权衡。

🏷 关键词

📄 原文摘要

Toshitsugu Sakamoto1, Koichiro Okamoto1, Naoki Banno1, Shinji Ishida1, Kimihiko Ito1, Hiromitsu Hada1, Noboru Sakimura1, Tadahiko Sugibayashi1, Masato Motomura2 1 NEC, Sagamihara, Japan, NEC, Kawasaki, Japan 2 Programmable devices such as SRAM-based FPGAs have the major challenges of power consumption and circuit area due to the excessive standby leakage current and the threshold voltage variation in highly scaled SRAM. Back-end-of-line (BEOL) device, which is integrated in the interconnect layers, is attractive for reducing the performance gap between FPGA and cell-based ASIC [1-4]. In this paper, we demonstrate the fundamental operations of a programmable cell array and a 32×32 crossbar switch using a nonvolatile and rewritable solid-electrolyte switch (nanobridge or NB). A 72% reduction in chip-area compared with that of a standard-cell-based design is achieved on a 90nm CMOS platform.

👥 作者与机构

Makoto Miyamura1, Shogo Nakaya2, Munehiro Tada1,