An 8MB Level-3 Cache in 32nm SOI with ColumnSelect Aliasing

📋 论文概要

本文介绍了一款在32nm SOI工艺上实现的8MB三级缓存，用于高性能多核处理器。通过采用ColumnSelect Aliasing技术，优化了缓存密度、产量和测试时间，同时降低了功耗。

💡 主要创新点

• 提出ColumnSelect Aliasing技术，有效提高缓存密度和良率。
• 采用多种电路技术降低功耗，满足性能功耗比目标。
• 针对大规模缓存优化测试时间，降低制造成本。

🏷 关键词

📄 原文摘要

Chris Helt1, Ryan Freese1, Tommy Miles1, Anita Karegar1, Russell Schreiber2, Bryan Schneller1, John Wuu1 1 AMD, Fort Collins, CO, AMD, Austin, TX 2 High-performance multi-core processors require efficient multi-level cache hierarchies to meet high-bandwidth data requirements. Because level-3 (L3) cache is typically the largest cache on the die, the drive to lower cost places pressure on density, yields, and test time. Performance-per-watt goals and total power constraints also compel a variety of circuit techniques to reduce power. The nextgeneration server processor codenamed “Orochi”, implemented on a 32nm high-k metal-gate SOI process with 11 metal layers, consists of four 2-core modules using AMD’s next-generation architecture, code named “Bulldozer”, with 2MB of dedicated L2 cache per module and an 8MB shared L3 cache [1]. The L3 cache is divided into 4 independent 2MB subcaches, shown in

👥 作者与机构

Don Weiss1, Michael Dreesen1, Michael Ciraula1, Carson Henrion1,