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提出一种差分ADC驱动放大器，采用0.18µm SiGe BiCMOS工艺，通过NPN-heavy电路和前馈嵌套米勒架构，在3.3V供电下实现108dBc IM3@100MHz，用于驱动高速高精度ADC，解决了传统工艺无法在先进节点实现的问题。
method of driving 1st and 2nd Nyquist zone signals into 100 to 500 Ms/s 12 to 16 bit ADCs. Previously the best performance (95dBc IM3 at 100MHz [1]) came from designs in dielectrically isolated (DI) Silicon Germanium complementary bipolar (CB) processes [2]. These have not been developed at the 0.18µm geometry node, as the cost of shrinking these esoteric processes is not justified by the low volume markets they serve. Here 108dBc IM3 at 100MHz is obtained using a 0.18µm SiGe NPN-only RF BiCMOS. NPN-heavy circuits and a feedforward nested Miller architecture achieve this at 3.3V supply voltage and 36mA total supply current. To achieve over 100dB of third-order linearity above 100 MHz requires both linear amplifying stages and copious loop gain. Without complementary PNPs, amplifying stages have 40dB or less DC open loop gain, limiting lower frequency (<100MHz) performance. Multipath nested Miller compensation (MNMC) [3]
Intersil, Harlow, United Kingdom, Fully differential (operational) amplifiers (FDA) have become the preferred