A 1.0625-to-14.025Gb/s Multimedia Transceiver with Full-rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40nm CMOS

📋 论文概要

该论文设计了一款速率范围从1.0625到14.025Gb/s的多媒体收发器，采用全速率源串联端接（SST）发送驱动和浮动抽头判决反馈均衡器（DFE），解决了长距离物理介质（如背板、铜缆和光模块）上的码间干扰、串扰和反射等挑战。

💡 主要创新点

• 提出全速率源串联端接发送驱动，实现高速率下的低功耗和信号完整性。
• 采用浮动抽头DFE结构，有效消除长距离信道中的码间干扰。

🏷 关键词

📄 原文摘要

Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang LSI, Milpitas, CA A robust transceiver designed for NRZ signaling beyond 10Gb/s over long-range physical media (including electrical backplanes, copper cables and optical modules) must contend with significant challenges from insertion loss, crosstalk, and reflection. For inter-symbol interference (ISI) cancellation, half-rate decision-feedback equalizer (DFE) with unrolled first tap [1-3] is widely used to avoid noise amplification and to relax timing for data sampling/feedback. However, tap-unrolling increases slicer count and entails half-rate multiplexers eating into timing margin. To remove reflection-induced ISI due to impedance discontinuities in the media, the DFE must cover tap positions higher than 30UI wh

👥 作者与机构

Shaolei Quan, Freeman Zhong, Wing Liu, Pervez Aziz, Tai Jing,